AD7367-5 Analog Devices, AD7367-5 Datasheet
AD7367-5
Specifications of AD7367-5
Related parts for AD7367-5
AD7367-5 Summary of contents
Page 1
... Each device contains two ADCs, which are both preceded by a 2-channel multiplexer, and a low noise, wide bandwidth, track-and-hold amplifier. The AD7366-5/AD7367-5 are fabricated on the Analog Devices, Inc., industrial CMOS process (iCMOS®) a technology platform combining the advantages of low and high voltage CMOS ...
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... AD7366-5/AD7367-5 to ADSP-218x ...................................... 24 AD7366-5/AD7367-5 to ADSP-BF53x ................................... 25 AD7366-5/AD7367-5 to TMS320VC5506 ............................. 25 AD7366-5/AD7367-5 to DSP563xx......................................... 26 Application Hints ........................................................................... 27 Layout and Grounding .............................................................. 27 Evaluating the AD7366-5/AD7367-5 ...................................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 Rev Page ...
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... MΩ 250 kΩ 1.2 MΩ Rev Page AD7366-5/AD7367 500 kSPS; f SAMPLE SCLK Test Conditions/Comments kHz sine wave kHz kHz @ 3 dB, ±10 V range @ 0.1 dB, ±10 V range Guaranteed no missed codes to 12 bits ±5 V and ±10 V analog input range ...
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... AD7366-5/AD7367-5 Parameter REFERENCE INPUT/OUTPUT Reference Output Voltage 3 Long-Term Stability 1 Output Voltage Hysteresis Reference Input Voltage Range DC Leakage Current Input Capacitance Output Impedance CAP CAP Reference Temperature Coefficient V Noise REF LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, V ...
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... AD7367-5 SPECIFICATIONS 2.5 V internal/external −40°C to +85°C, unless otherwise noted. REF A Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 1 Signal-to-Noise (+ Distortion) Ratio (SINAD) 1 Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) 1 Intermodulation Distortion (IMD) ...
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... AD7366-5/AD7367-5 Parameter REFERENCE INPUT/OUTPUT 3 Reference Output Voltage Long-Term Stability 1 Output Voltage Hysteresis Reference Input Voltage Range DC Leakage Current Input Capacitance Output Impedance CAP CAP Reference Temperature Coefficient V Noise REF LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, V ...
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... DRIVE Test Conditions/Comments Conversion time, internal clock. CONVST falling edge to BUSY falling edge. For the AD7367-5. For the AD7366-5. Frequency of serial read clock. Minimum quiet time required between the end of serial read and the start of the next conversion. Minimum CONVST low pulse. ...
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... AD7366-5/AD7367-5 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter V to AGND, DGND AGND, DGND DGND DRIVE AGND, DGND DGND AGND DRIVE AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND ...
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... SCLK cycle are required for the AD7367-5. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366-5 and 14 bits for the AD7367-5 and is provided MSB first held low for a further 12 SCLK cycles for the AD7366 SCLK cycles for the AD7367-5, on either D ...
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... D 20 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366-5/AD7367-5. 21 CNVST Conversion Start, Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes into hold mode and the conversion is initiated ...
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... T = 25°C, unless otherwise noted. A 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 INTERNAL REFERENCE –1.0 0 2000 4000 6000 8000 10000 CODE Figure 3. AD7367-5 Typical DNL 2.0 1.5 1.0 0.5 0 –0.5 –1.0 V –1.5 INTERNAL REFERENCE –2.0 0 2000 4000 6000 8000 10000 CODE Figure 4. AD7367-5 Typical INL 0 V –20 ...
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... AD7366-5/AD7367-5 –70 –75 –80 ±5V RANGE –85 –90 –95 –100 –105 INTERNAL REFERENCE –110 0 100 200 300 FREQUENCY OF INPUT NOISE (kHz) Figure 9. Channel-to-Channel Isolation 110000 106091 CODES 31 CODES 100000 90000 80000 70000 60000 50000 40000 30000 20000 10000 0 8191 ...
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... Figure 15. Power vs. Sampling Frequency in Normal Mode OUT = 5V 15V 500kSPS S 2000 2500 ) and OUT Rev Page AD7366-5/AD7367 5V 15V –15V DRIVE f = 500kSPS S INTERNAL REFERENCE ±5V RANGE 0V TO +10V RANGE ±10V RANGE ...
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... The figure given is the typical across all four channels for the AD7366-5/AD7367-5 (see the Figure 9 for more information). Intermodulation Distortion ...
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... It is expressed in ppm using the following equation REF V ( ppm ) HYS where: V (25° 25°C. REF REF V (T_HYS) is the maximum change of V REF or T_HYS−. Rev Page AD7366-5/AD7367-5 ° − HYS ) × 6 REF 10 ° REF ...
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... CIRCUIT INFORMATION The AD7366-5/AD7367-5 are fast, dual, 2-channel, 12-/14-bit, bipolar input, simultaneous sampling, serial ADCs. The AD7366-5/AD7367-5 can accept bipolar input ranges of ±10 V and ±5 V. They can also accept unipolar input range. The AD7366-5/AD7367-5 require V supplies for the high voltage analog input structure ...
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... DD SS analog input structures. These supplies must be greater than or equal to ±5 V (see Table 7 for the requirements on these supplies). The AD7366-5/AD7367-5 require a low voltage 4. 5. supply to power the ADC core supply for digital power, and interface power ...
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... Figure 20. Typical Connection Diagram for ±10 V Range Using Internal Reference TYPICAL CONNECTION DIAGRAM Figure 20 shows a typical connection diagram for the AD7366-5/ AD7367-5. In this configuration, the AGND pin is connected to the analog ground plane of the system, and the DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7366-5/AD7367-5 accept bipolar single-ended signals ...
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... The reference buffer requires 70 μs to power up and charge the 680 nF decoupling capacitor during the power-up time. The AD7366-5/AD7367-5 is specified for a 2 reference range. When reference is selected, the ranges are ±12 V, ±6 V, and +12 V. For these ranges, the V must be greater than or equal to the +12 V and − ...
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... AD7367-5. The D to three-state only when CS is brought high left low for a further 12 SCLK cycles for the AD7366 SCLK cycles for the AD7367-5, the result from the other on-chip ADC is also accessed on the same D Figure 28 ...
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... The D CS return to three-state once is brought back to logic high. To exit full power-down and to power up the AD7366-5/ AD7367-5, a rising edge of CNVST is required. After the required power-up time has elapsed, CNVST may be brought low again to initiate another conversion, as shown in Figure 24 CNVST t BUSY ...
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... CS takes the bus out of three-state and clocks out the MSB of the conversion result. The data stream consists of 12 bits of data for the AD7366-5 and 14 bits of data for the AD7367-5, MSB first. The first bit of the conversion result is valid on the first SCLK falling edge after the CS falling edge ...
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... Line with 24 SCLKs for the AD7366-5 OUT DB1 DB0 DB13 DB12 Line with 28 SCLKs for the AD7367-5 OUT Rev Page AD7366-5/AD7367-5 24 DB1 DB0 B B THREE- STATE 28 DB1 DB0 B B THREE- STATE ...
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... V DD the ADSP-218x when the conversion is complete. The conversion results can then be read from the AD7366-5/AD7367-5 using a read operation. When an interrupt is received on IRQn from the BUSY signal, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and, therefore, the reading of data ...
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... RCLKO RFS0 RXINPUTS PFn DR0SEC V DD *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 31. Interfacing the AD7366-5/AD7367-5 to the TMS320VC5506 Table 15. Serial Port Control Register Setup SPC SPC0 SPC1 The V DRIVE supply voltage as that of the TMS320VC5506. This allows the ADC to operate at a higher voltage than its serial interface and, therefore, the TMS320VC5506, if necessary ...
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... The frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1, while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an input. The V DSP563xx* AD7367-5 takes the same supply voltage as that of the DSP563xx. This allows the ADC to operate at a higher voltage than its SCK0 serial interface and, therefore, the DSP563xx, if necessary. ...
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... AD7366-5/AD7367-5 should be connected to the AGND plane. Digital and analog ground pins should be joined in only one place. If the AD7366-5/AD7367-5 are in a system where multiple devices require an AGND and DGND connection, the connection should still be made at only one point. A star point should be established as close as possible to the ground pins on the AD7366-5/AD7367-5 ...
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... AD7366-5/AD7367-5 OUTLINE DIMENSIONS PIN 1 0.15 0.05 0.10 COPLANARITY ORDERING GUIDE Model Temperature Range 1 AD7366BRUZ-5 −40°C to +85°C AD7366BRUZ-5-RL7 1 −40°C to +85°C 1 AD7366BRUZ-5500RL7 −40°C to +85°C AD7367BRUZ-5 1 −40°C to +85°C 1 AD7367BRUZ-5-RL7 −40°C to +85°C AD7367BRUZ-5500RL7 1 −40°C to +85° RoHS Compliant Part ...