STA308 STMicroelectronics, STA308 Datasheet

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... C Control April 2010 TQFP64 ORDERING NUMBER: STA308 DESCRIPTION The STA308 is a single chip solution for digital audio processing and control in multi-channel applications. It provides output capabilities for DDX tal Amplification). In conjunction with a DDX device, it provides high-quality, high-efficiency, all digital amplification. The device is extremely versatile allowing for input of most digital formats including 6 ...

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... STA308 BLOCK DIAGRAM LRCKI BICKI SERIAL SDI12 DATA SDI34 IN SDI56 SDI78 CHANNEL MAPPING SYSTEM TIMING PLLB PLL XTI CKOUT Figure 1. Signal Flow Diagram Channels 1-8 1st Stage Interpolation Output 8 Inputs From I2S Channel Mapping 2/33 SA SCL SDA MVO OVERSAMPLING SYSTEM CONTROL ...

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... Input I2S Serial Data Channels 3 & Input I2S Serial Data Channels 1 & Inputs I2C Left/Right Clock I Inputs I2C Serial Clock I Global Reset I PLL Bypass I Select Address (I2C) I/O I2C Serial Data I I2C Serial Clock STA308 48 OUT2_A 47 OUT2_B 46 VDD 45 GND 44 VDD3 43 OUT3_A 42 OUT3_B 41 OUT4_A ...

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... STA308 PIN FUNCTION (continued) PIN NAME 20 XTI 21 FILTER_PLL 22 VDDA 23 GNDA 25 CKOUT 29 OUT8_B 30 OUT8_A 31 OUT7_B 32 OUT7_A 33 OUT6_B 34 OUT6_A 38 OUT5_B 39 OUT5_A 40 OUT4_B 41 OUT4_A 42 OUT3_B 43 OUT3_A 47 OUT2_B 48 OUT2_A 49 OUT1_B 50 OUT1_A 51 EAPD 55 BICKO 56 LRCKO 57 SDO_12 58 SDO_34 62 SDO_56 63 SDO_78 64 PWDN 4/33 TYPE DESCRIPTION I Crystal Oscillator Input (Clock Input) PLL Filter PLL 2 ...

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... Symbol R Thermal resistance Junction to Ambient thj-amb RECOMMENDED DC OPERATING CONDITIONS Symbol V I/O Power Supply DD_3.3 V Logic Power Supply DD_2.5 T Operating Junction Temperature j Parameter Parameter Parameter STA308 Value Unit -0 -0.5 to 3.3 V -0.5 to (VDD+0.5) V -0.5 to (VDD+0.3) V °C -40 to +150 °C -20 to +85 Value Unit °C/W ...

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... STA308 ELECTRICAL CHARACTERISTCS (V wise specified) GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input no pull- High Level Input no pull-down ih I Tristate output leakage without OZ pullup/down V Electrostatic Protection esd Note 1: The leakage currents are generally very small, < 1na. The values given here are maximum after an electrostatic stress on the pin. ...

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... EAPD goes low ~30ms later. 2.0 II2C BUS SPECIFICATION The STA308 supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave ...

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... The 8th bit (LSB) identifies read or write operation RW, this bit is set read mode and 0 for write mode. After a START condition the STA308 identifies on the bus the device address and if a match is found, it acknowl- edges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address ...

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... C1V3 C1V2 C1V1 C2V3 C2V2 C2V1 C3V3 C3V2 C3V1 C4V3 C4V2 C4V1 C5V3 C5V2 C5V1 C6V3 C6V2 C6V1 C7V3 C7V2 C7V1 STA308 ACK STOP NO ACK STOP D0 MCS0 DSPB OM0 C12BO MIXE PWMD MMute MV0 C1M C1V0 C2V0 C3V0 C4V0 C5V0 C6V0 ...

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... STA308 10h C8Vol C8V7 11h C12im 12h C34im 13h C56im 14h C78im 15h C1234ls C4LS1 16h C5678ls C8LS1 17h L1ar L1R3 18h L1atrt L1AT3 19h L2ar L2R3 1Ah L2atrt L2AT3 1Bh Tone TTC3 1Ch Cfaddr CFA7 1Dh B2cf1 C1B23 1Eh B2cf2 ...

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... R R/W 0 The STA308 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz. Therefore the internal clock will be: – 65.536Mhz for 32kHz – 90.3168Mhz for 44.1khz, 88.2kHz, and 176.4kHz – 98.304Mhz for 48kHz, 96kHz, and 192kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IRx (In- put Rate) register bits ...

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... NAME 6 R/W 0 HPE Channels 7 and 8 of the STA308 have the option to be processed for headphones. The headphone output can then be driven using an appropriate output device. This signal is a fully differential 3-wire drive called DDX Headphone 3.0.5 Max Power Correction BIT R/W ...

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... RST R/W 0 The STA308 features a configurable digital serial audio interface. The settings of the SAIx bits determine how the input to this interface is interpreted. Six formats are accepted. Table 3. Interface format as a function of SAI bits. SAI(2..0) Interface Format 000 001 Left-Justified Data ...

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... STA308 3.1.3 Serial Audio Input Interface First Bit BIT R/W RST NAME 5 R/W 0 SAIFB 3.1.4 Zero-Crossing Volume Enable BIT R/W RST NAME 6 R/W 1 ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings, "zipper noise" is eliminated 3.1.5 Dynamic Range Compression/Anti-Clipping Bit ...

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... BIT R/W RST 7 R/W 0 The STA308 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage 3.3 Configuration Register D (address 03h) BIT D7 D6 NAME ...

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... R R/W 0 The STA308 features a configurable digital serial audio interface. The settings of the SAIx bits determine how the output to this interface is interpreted. Six formats are accepted. 16/33 Biquad Link : 0 – Each Channel uses coefficient values 1- Each Channel uses Channel 1 coefficient values ...

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... AME The STA308 features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended to be used when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83dB in this mode, which is still greater than the SNR of AM radio. ...

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... STA308 3.7 Master Volume Register (address 07h) BIT D7 D6 NAME MV7 MV6 RST 1 3.8 Channels 1,2,3,4,5,6,7,8 Mute (address 08h) BIT D7 D6 NAME C8M C7M RST 0 3.9 Channel 1 Volume (address 09h) BIT D7 D6 NAME C1V7 C1V6 RST 0 3.10 Channel 2 Volume (address 0Ah) ...

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... RST 0 The Volume structure of the STA308 consists of individual volume registers for each channel and a master vol- ume register that provides an offset to each channels volume setting. The individual channel volumes are ad- justable in 0.5dB steps from +24dB to -103dB example if C5V = 0Bh or +18.5dB and MV = 21h ...

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... STA308 Channel Volume as a function of CxV(7..0) CxV(7..0) 00000000(00h) 00000001(01h) 00000010(02h) … 00101111(2Fh) 00110000(30h) 00110001(31h) … 11111110(FEh) 11111111(FFh) 3.17 Channel Input Mapping Channels 1 & 2 (address 11h) BIT D7 D6 NAME C2IM2 RST 3.18 Channel Input Mapping Channels 3 & 4 (address 12h) BIT D7 D6 NAME ...

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... Channel 1 001 Channel 2 010 Channel 3 011 Channel 4 100 Channel 5 101 Channel 6 110 Channel 7 111 Channel 8 STA308 Output Phasing CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 3.21 Channel Limiter Select Channels 1,2,3,4 (address 15h) BIT D7 D6 NAME C4LS1 C4LS0 RST 0 3 ...

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... A limiter is basically a variable gain device, where the amount of gain applied depends on the input signal level. As the name implies, compression limits the dynamic range of the signal. The STA308 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of the input signal to prevent the out- puts from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environ- ment such as a night-time listening mode which is often needed for DVDs ...

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... DDX amplifier. Since gain can be added digitally within the STA308 it is possible to exceed 0dBFS or any other LxAT setting. When this occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter ...

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... STA308 Table 9. Limiter Release Rate and Uncompression Threshold as a function of LxR bits LxR(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 10. Limiter Attack Threshold as a function of LxAT bits. LxAT(3..0) AC(dB relative to FS) ...

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... RST 0 The STA308 contains bass and treble tone control adjustments. These are selectable from +12dB to -12dB of boost or cut. These are 1st order shelving filters with a corner frequency of 150Hz for bass and 3kHz for treble. Any gain introduced in the tone controls will carry through to the volume and limiting block without saturation. ...

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... STA308 3.28 Coefficient Address Register (address 1Ch) BIT D7 D6 NAME CFA7 CFA6 RST 0 3.29 Coefficient b2 Data Register Bits 23..16 (address 1Dh) BIT D7 D6 NAME C1B23 C1B22 RST 0 3.30 Coefficient b2 Data Register Bits 15..8 (address 1Eh) BIT D7 D6 NAME C1B15 C1B14 RST 0 3 ...

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... C3B11 C3B10 C3B9 C3B3 C3B2 C3B1 C4B19 C4B18 C4B17 C4B11 C4B10 C4B9 C4B3 C4B2 C4B1 C5B19 C5B18 C5B17 C5B11 C5B10 C5B9 C5B3 C5B2 C5B1 STA308 D0 C3B8 0 D0 C3B0 0 D0 C4B16 0 D0 C4B8 0 D0 C4B0 0 D0 C5B16 0 D0 C5B8 0 D0 C5B0 0 27/33 ...

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... NAME RST Coefficients for EQ and Bass Management are handled internally in the STA308 via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers is dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the writing of the coefficient(s) to RAM ...

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... When using this technique, the 8-bit address would specify the address of the biquad b2 coefficient (e. 10, 15, …, 50, … 195 decimal), and the STA308 will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. ...

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... STA308 Post-Scale The STA308 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiply. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. All chan- nels can use the channel 1 by setting the post-scale link bit ...

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... inch TYP. MAX. 0.063 0.006 0.055 0.057 0.472 0.480 0.394 0.401 0.295 0.0197 0.472 0.480 0.394 0.401 0.295 0.0393 TQFP64 ( 1.4mm) 0.0031 TQFP64 STA308 OUTLINE AND MECHANICAL DATA 0.08mm ccc Seating Plane C K 0051434 E 31/33 ...

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... STA308 4.0 REVISION HISTORY Table 13. Revision History Date Revision April 2004 30-Apr-2010 32/33 2 Updates not recorded 3 Removed "Preliminary data" status from cover page Description of Changes ...

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