LPC1774FBD208 NXP Semiconductors, LPC1774FBD208 Datasheet - Page 116
![The LPC1774 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz](/photos/41/52/415298/sot459-1_3d_sml.gif)
LPC1774FBD208
Manufacturer Part Number
LPC1774FBD208
Description
The LPC1774 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1774FBD144.pdf
(120 pages)
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18. Revision history
Table 37.
LPC178X_7X
Objective data sheet
Document ID
LPC178X_7X v.3
Modifications:
LPC178X_7X v.2
Modifications:
LPC178X_7X v.1
Revision history
Release date
20111227
20110527
20110524
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Removed BOOT function from pin P3[14].
I
Maximum SDRAM clock of 80 MHz specified in
Power consumption data added
Removed parameter Z
Specified maximum value for parameter C
Specified setting of boost bits in
USB connection diagrams updated
Current drain condition on battery supply specified in
Table note 10
ADC characteristics updated
Section 14.6 “Reset pin configuration for RTC operation”
EEPROM size for parts LPC1774 corrected in
Changed function LCD_VD[5] on pin P0[10] to Reserved.
Changed function LCD_VD[10] on pin P0[11] to Reserved.
Changed function LCD_VD[13] on pin P0[19] to Reserved.
Changed function LCD_VD[14] on pin P0[20] to Reserved.
ADC interface model updated (see
Symbol names in
Reserved functions added in
Added function LCD_VD[5] to pin P0[10].
Added function LCD_VD[10] to pin P0[11].
Added function LCD_VD[13] to pin P0[19].
Added function LCD_VD[14] to pin P0[20].
Added function U4_SCLK to pin P0[21].
Added function
Added function MOSI to pin P5[0].
Added function SSP2_MISO to pin P5[1].
Added EMC dynamic characteristics.
BAT
and I
DD(REG)(3V3)
All information provided in this document is subject to legal disclaimers.
in
Data sheet status
Objective data sheet
Objective data sheet
Objective data sheet
Rev. 3 — 27 December 2011
Table 13
Table 3
updated for Deep power-down mode in
DRV
updated.
to
in
Table 5
Table
(Table
Table
(Figure 9
Table
13.
Table 32
3.
(Figure 33
31).
abbreviated.
14,
and
L
Table note 5
in
Change notice
-
and
-
-
Table 33
Table 2
32-bit ARM Cortex-M3 microcontroller
Figure
to
Section
Figure
Figure
Section
10).
and
and in
and remove typical value.
30.
2,
36).
added.
Table
Figure
Table
7.33.6.
Table
LPC178x/7x
Supersedes
-
18, and
-
-
1.
13.
13,
© NXP B.V. 2011. All rights reserved.
Table note 6
Table
19.
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