BUK9MPP-65PLL NXP Semiconductors, BUK9MPP-65PLL Datasheet
BUK9MPP-65PLL
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BUK9MPP-65PLL Summary of contents
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... BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET Rev. 03 — 15 July 2010 1. Product profile 1.1 General description Dual N-channel enhancement mode field-effect power transistor in SO20. Device is manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring very low on-state resistance, integrated current sensing transistors and over temperature protection diodes ...
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... Graphic symbol SOT163-1 (SO20) Description plastic small outline package; 20 leads; body width 7.5 mm All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET FET1 FET2 G1 IS1 S1 KS1 C1 G2 IS2 S2 KS2 C2 ...
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... HBM 100 pF 1.5 kΩ; pins 3, 16 and 20 to pins 1, 2, 17, 18 and 19 shorted All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET Min Max - 65 - ...
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... All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET der 100 150 Normalized total power dissipation as a function of solder point temperature, FET1 and FET2 ...
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... Safe operating area; continuous and peak drain currents as a function of drain-source voltage BUK9MPP-65PLL Product data sheet Limit DSon All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET 001aal756 = 10 μ 100 μ 100 (V) DS © ...
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... Figure 7; see Figure 6 mounted on a printed-circuit board; one channel conducting; 400 mm² copper heat sink area; see Figure 8 All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET Min Typ Max - - ...
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... Fig 8. PCB used for thermal tests; heat sink area 400 mm² All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET 003aac472 (1) (2) 100 200 300 ...
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... Transient thermal impedance from junction to ambient as a function of pulse duration BUK9MPP-65PLL Product data sheet −5 −4 −3 −2 − All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET 001aal805 t p δ ...
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... G(ext Ω Ω R G(ext) from pin to center of die All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET Min Typ Max 1 ...
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... A/µ - 003aae482 (V) GS Fig 11. Forward transconductance as a function of All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET Min Typ - ...
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... Fig 13. Output characteristics: drain current as a 001aam030 V GS(th) max (V) GS Fig 15. Gate-source threshold voltage as a function of All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET 120 I D (A) 10 100 ...
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... V (V) GS Fig 19. Temperature sense diode forward voltage as a function of junction temperature; typical values, FET1 and FET2 All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET 2.5 3.0 3.5 4.0 4 ...
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... G Fig 21. Input, output and reverse transfer capacitances 120 0.5 1 All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET (pF function of drain-source voltage; typical ...
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... REFERENCES JEDEC JEITA MS-013 All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET θ detail ...
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... NXP Semiconductors 8. Revision history Table 7. Revision history Document ID Release date BUK9MPP-65PLL v.3 20100715 • Modifications: Various changes to content. BUK9MPP-65PLL v.2 20100617 BUK9MPP-65PLL Product data sheet Data sheet status Change notice Product data sheet - Product data sheet - All information provided in this document is subject to legal disclaimers. ...
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... All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET © NXP B.V. 2010. All rights reserved ...
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... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 July 2010 BUK9MPP-65PLL Dual TrenchPLUS FET Logic Level FET © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: BUK9MPP-65PLL All rights reserved. Date of release: 15 July 2010 ...