STM32F050K6 STMicroelectronics, STM32F050K6 Datasheet
STM32F050K6
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STM32F050K6 Summary of contents
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... One SPI (18 Mbit/s) with programmable bit frame, with I multiplexed Table 1. Device summary Reference STM32F050x4 STM32F050K4, STM32F050C4 STM32F050x6 STM32F050K6, STM32F050C6 Doc ID 022717 Rev 2 STM32F050x4 STM32F050x6 Data brief UFQFPN32 5x5 2 S interface Part number 1/34 www.st.com ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F050xx 3.17.3 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F050xx List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STM32F050xx family incorporates the high-performance ARM Cortex™-M0 32-bit RISC core operating MHz maximum frequency, high-speed embedded memories (Flash memory Kbytes and SRAM Kbytes), and an extensive range ...
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STM32F050xx Table 2. STM32F050xx family device features and peripheral counts Peripheral Flash (Kbytes) SRAM (Kbytes) Advanced control Timers General purpose SPI (I2S) Comm interfaces USART 12-bit synchronized ADC (number of channels) GPIOs Max. CPU frequency Operating voltage ...
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Device overview 2 Device overview Figure 1. Block diagram 8/9 Doc ID 022717 Rev 2 STM32F050xx ...
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STM32F050xx Figure 2. Clock tree Doc ID 022717 Rev 2 Device overview 9/9 ...
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Functional overview 3 Functional overview ® 3.1 ARM Cortex The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with ...
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STM32F050xx 3.4 Direct memory access controller (DMA) The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each ...
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Functional overview Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz. 3.8 Boot modes At startup, the boot pin and ...
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STM32F050xx 3.9.3 Voltage regulator The regulator has three operating modes: main (MR), low power (LPR) and power down. ● used in normal operating mode (Run) ● LPR can be used in Stop mode where the power demand is ...
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Functional overview The RTC is an independent BCD timer/counter. Its main features are the following: ● Calendar with subsecond, seconds, minutes, hours ( format), week day, date, month, year, in BCD (binary-coded decimal) format. ● Automatically correction for ...
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STM32F050xx 3.12.1 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. ...
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Functional overview TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output. The TIM16 and TIM17 timers can work together via the Timer Link feature for synchronization or event chaining. TIM16, and TIM17 have ...
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STM32F050xx Table 4. Comparison of I2C analog and digital filters Pulse width of suppressed spikes Benefits Drawbacks In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications ...
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Functional overview 3.16 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down peripheral alternate function. Most of the GPIO pins are ...
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STM32F050xx 4 Pinouts and pin description Figure 3. LQFP48 48-pin package pinout Figure 4. UFQFPN32 32-pin package pinout Doc ID 022717 Rev 2 Pinouts and pin description 19/34 ...
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Pinouts and pin description Table 5. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Alternate functions Pin functions Additional functions 20/34 Abbreviation Unless otherwise specified in brackets below the pin name, the pin function ...
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STM32F050xx Table 6. Pin definitions Pin number Pin name (function after reset) 1 VBAT 2 PC13 PC14-OSC32_IN 3 (PC14) PC15- OSC32_OUT 4 (PC15) PF0-OSC_IN 5 2 (PF0) PF1-OSC_OUT 6 3 (PF1 NRST 8 0 VSSA 9 5 VDDA ...
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Pinouts and pin description Table 6. Pin definitions (continued) Pin number Pin name (function after reset PB2 21 PB10 22 PB11 23 0 VSS 24 17 VDD 25 PB12 26 PB13 27 PB14 28 PB15 29 18 PA8 ...
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STM32F050xx Table 6. Pin definitions (continued) Pin number Pin name (function after reset PB7 44 31 BOOT0 45 32 PB8 47 0 VSS 48 1 VDD 1. PC13, PC14 and PC15 are supplied through the power switch. Since ...
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Table 7. Alternate functions selected through GPIOA_AFR registers for port A Pin name AF0 AF1 PA0 PA1 EVENTOUT PA2 PA3 SPI1_NSS/ PA4 I2S1_WS SPI1_SCK/ PA5 I2S1_CK SPI1_MISO/ PA6 TIM3_CH1 I2S1_MCK SPI1_MOSI/ PA7 TIM3_CH2 I2S1_SD PA8 MCO USART1_CK PA9 USART1_TX PA10 ...
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Table 8. Alternate functions selected through GPIOB_AFR registers for port B Pin name AF0 PB0 EVENTOUT PB1 TIM14_CH1 PB2 PB3 SPI1_SCK/I2S1_CK PB4 SPI1_MISO/I2S1_MCK PB5 SPI1_MOSI/I2S1_SD PB6 USART1_TX PB7 USART1_RX PB8 PB9 IR_OUT PB10 PB11 EVENTOUT PB12 PB13 PB14 PB15 AF1 ...
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Memory mapping 5 Memory mapping Figure 5. STM32F050xx memory map 26/28 Doc ID 022717 Rev 2 STM32F050xx ...
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STM32F050xx Table 9. STM32F050x peripheral register boundary addresses Bus AHB2 AHB1 APB Boundary address 0x4800 1800 - 0x5FFF FFFF 0x4800 1400 - 0x4800 17FF 0x4800 1000 - 0x4800 13FF 0x4800 0C00 - 0x4800 0FFF 0x4800 0800 - 0x4800 0BFF 0x4800 ...
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Memory mapping Table 9. STM32F050x peripheral register boundary addresses (continued) Bus APB 28/28 Boundary address 0x4000 7C00 - 0x4000 7FFF 0x4000 7800 - 0x4000 7BFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 5C00 - 0x4000 6FFF ...
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STM32F050xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are ...
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Package characteristics Figure 6. LQFP48 – 7mm, 48-pin low-profile quad flat package outline Pin 1 identification Drawing is not to scale. 2. Dimensions are in ...
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STM32F050xx Figure 8. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (1)(2)( Seating plane Pin # 0.30 D2 Bottom ...
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Ordering information scheme 7 Ordering information scheme For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Example: Device family STM32 = ...
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STM32F050xx 8 Revision history Table 12. Document revision history Date 09-Feb-2012 24-Feb-2012 Revision 1 Initial release Corrected list of peripherals in 2 Updated Table 7 and Doc ID 022717 Rev 2 Revision history Changes Section 1 Table 8 33/33 ...
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