STM32W108CB STMicroelectronics, STM32W108CB Datasheet - Page 84

• Manufacturer Part Number: STM32W108CB
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CB

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

Serial interfaces
9.4.3
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Characters received are stored in the receive FIFO. Receiving characters sets the
SC_SPIRXVAL bit in the SCx_SPISTAT register, to indicate that characters can be read
from the receive FIFO. Characters received while the receive FIFO is full are dropped, and
the SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware
generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error
condition until the receive FIFO is drained. Once the DMA marks a receive error, two
conditions will clear the error indication: setting the appropriate SC_TX/RXDMARST bit in
the SCx_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded.
Receiving a character causes the serial transmission of a character pulled from the transmit
FIFO. When the transmit FIFO is empty, a transmit underrun is detected (no data in transmit
FIFO) and the INT_SCTXUND bit in the INT_SCxFLAG register is set. Because no
character is available for serialization, the SPI serializer retransmits the last transmitted
character or a busy token (0xFF), determined by the SC_SPIRPT bit in the SCx_SPICFG
register.
When the transmit FIFO and the serializer are both empty, writing a character to the transmit
FIFO clears the SC_SPITXIDLE bit in the SCx_SPISTAT register. This indicates that not all
characters have been transmitted. If characters are written to the transmit FIFO until it is full,
the SC_SPITXFREE bit in the SCx_SPISTAT register is cleared. Shifting out a transmit
character to the MISO pin causes the SC_SPITXFREE bit in the SCx_SPISTAT register to
get set. When the transmit FIFO empties and the last character has been shifted out, the
SC_SPITXIDLE bit in the SCx_SPISTAT register is set.
The SPI slave controller must guarantee that there is time to move new transmit data from
the transmit FIFO into the hardware serializer. To provide sufficient time, the SPI slave
controller inserts a byte of padding at the start of every new string of transmit data. After
slave select asserts and the SC_SPIRXVAL bit in the SCx_SPISTAT register gets set at
least once, the following operation holds true until slave select deasserts. Whenever the
transmit FIFO is empty and data is placed into the transmit FIFO, either manually or through
DMA, the SPI hardware inserts a byte of padding onto the front of the transmission as if this
byte was placed there by software. The value of the byte of padding that is inserted is
selected by the SC_SPIRPT bit in the SCx_SPICFG register.
DMA
The DMA Channels section describes how to configure and use the serial receive and
transmit DMA channels.
When using the receive DMA channel and nSSEL transitions to the high (deasserted) state,
the active buffer's receive DMA count register (SCx_RXCNTA/B) is saved in the
SCx_RXCNTSAVED register. SCx_RXCNTSAVED is only written the first time nSSEL goes
high after a buffer has been loaded. Subsequent rising edges set a status bit but are
otherwise ignored. The 3-bit field SC_RXSSEL in the SCx_DMASTAT register records what,
if anything, was saved to the SCx_RXCNTSAVED register, and whether or not another
rising edge occurred on nSSEL.
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Doc ID 16252 Rev 13