STM32W108HB STMicroelectronics, STM32W108HB Datasheet - Page 91

• Manufacturer Part Number: STM32W108HB
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108HB

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
9.6.2
A UART character frame contains, in sequence:
●
●
●
●
●
Figure 12
on the options chosen for the character frame, the length of a character frame ranges from 9
to 12 bit times.
Note that asynchronous serial data may have arbitrarily long idle periods between
characters. When idle, serial data (TXD or RXD) is held in the high state. Serial data
transitions to the low state in the start bit at the beginning of a character frame.
Figure 12. UART character frame format
FIFOs
Characters transmitted and received by the UART are buffered in the transmit and receive
FIFOs that are both 4 entries deep (see
SC1_DATA register, it is pushed onto the transmit FIFO. Similarly, when software reads from
the SC1_DATA register, the character returned is pulled from the receive FIFO. If the
transmit and receive DMA channels are used, the DMA channels also write to and read from
the transmit and receive FIFOs.
Figure 13. UART FIFOs
TXD
RXD
The start bit
The least significant data bit
The remaining data bits
If parity is enabled, the parity bit
The stop bit, or bits, if 2 stop bits are selected.
or
RXD
shows the UART character frame format, with optional bits indicated. Depending
Idle time
Receive Shift Register
SC1_DATA (read)
Start
Bit
Data
Bit 0
Data
Bit 1
Doc ID 16252 Rev 13
Parity/Frame Errors
SC1_UARTSTAT
Data
Bit 2
UART Character Frame Format
(optional sections are in italics )
Data
Bit 3
Figure
Data
Bit 4
13). When software writes a character to the
Data
Bit 5
Transmit Shift Register
Data
Bit 6
SC1_DATA (write)
Data
Bit 7
Parity
Bit
Stop
Bit
TXD
Serial interfaces
Channel Access
Stop
CPU and DMA
Bit
IdleTime
Start Bit
Next
or
91/232