ST7263BH6 STMicroelectronics, ST7263BH6 Datasheet - Page 55
ST7263BH6
Manufacturer Part Number
ST7263BH6
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
Manufacturer
STMicroelectronics
Datasheet
1.ST7263BH6.pdf
(186 pages)
Specifications of ST7263BH6
4, 8, 16 Or 32 Kbytes Program Memory
high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection
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ST7263Bxx
Note:
11.1.4
11.1.5
11.1.6
Figure 26. Watchdog block diagram
Table 17.
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
Software Watchdog option
If Software Watchdog is selected by option byte, the watchdog is disabled following a reset.
Once activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
Hardware Watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Low power modes
WAIT instruction
No effect on Watchdog.
a
Max
Min
Watchdog timing (f
CR register initial value
f
CPU
WDGA
RESET
Doc ID 7516 Rev 8
C0h
FFh
CPU
T6
= 8 MHz)
T5
WATCHDOG CONTROL REGISTER (CR)
7-BIT DOWNCOUNTER
CLOCK DIVIDER
T4
÷49152
T3
T2
WDG timeout period (ms)
T1
393.216
6.144
On-chip peripherals
T0
55/186
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