STR711FR0 STMicroelectronics, STR711FR0 Datasheet - Page 15

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STR711FR0

Manufacturer Part Number
STR711FR0
Description
ARM-Based Flash microcontrollers with USB
Manufacturer
STMicroelectronics
Datasheet

Specifications of STR711FR0

5 Power Saving Modes
SLOW, WAIT, LPWAIT, STOP and STANDBY modes
Conversion Range
0 to 2.5 V

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STR71xF
Table 4.
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Pin n°
M4 N.C.
M2 N.C.
M3 DBGRQS
M5
M6 STDBY
M7 RSTIN
H5 N.C.
H6 N.C.
G6 V
K3 V
L4
K4 CKOUT
L5
K5 RTCXTI
L6
K6 V
J4
J5
J6
V
CK
P0.15/
WAKEUP
N.C.
RTCXTO
V
N.C.
33IO-PLL
SSIO-PLL
SSBKP
18BKP
18
STR710 pin description
Pin name
I/O
O
S
S
S
I
I
I
I
C
C
C
T
Input
C
S
S
T
T
T
T
X
8mA
4mA X
Output
X
X
X
X Reset input
X Stabilization for low power voltage regulator.
X
Supply voltage for digital I/O circuitry and for PLL
reference
Not connected (not bonded)
Ground voltage for digital I/O circuitry and for PLL
reference
Not connected (not bonded)
Debug Mode request input (active high)
Clock output (f
register in APB Bridge 2
Reference clock input
Port 0.15 Wakeup from Standby mode input.
Note: This port is input only.
Not connected (not bonded)
Realtime Clock input and input of 32 kHz
oscillator amplifier circuit
Output of 32 kHz oscillator amplifier circuit
Input: Hardware Standby mode entry input active
low. Caution: External pull-up to V
select normal mode.
Output: Standby mode active low output following
Software Standby mode entry.
Note: In Standby mode all pins are in high
impedance except those marked Active in Stdby
Not connected (not bonded)
Stabilization for low power voltage regulator.
Requires external capacitors of at least 1µF
between V
Note: If the low power voltage regulator is
bypassed, this pin can be connected to an
external 1.8V supply.
Not connected (not bonded)
Not connected (not bonded)
Stabilization for main voltage regulator. Requires
external capacitors of at least 10µF + 33nF
between V
function
reset)
(after
Main
4)
18BKP
18
and V
PCLK2
and V
SS18
) Note: Enabled by CKDIS
Alternate function
SS18BKP
. See
System architecture
Figure
. See
33
Figure
5.
required to
5.
15/78

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