ST72324LK2 STMicroelectronics, ST72324LK2 Datasheet - Page 127

• Manufacturer Part Number: ST72324LK2
• Description: 3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324LK2

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Figure 73. Typical Application with RESET pin
Notes:
1. Data guaranteed by design, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I
(I/O ports and control pins) must not exceed I
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current source on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
t
w(RSTL)out
t
t
Symbol
h(RSTL)in
g(RSTL)in
Required
EXTERNAL
R
CIRCUIT
V
V
V
V
I
hys
IO
ON
RESET
OL
IL
IH
IL
USER
max. level specified in
IO
current sunk must always respect the absolute maximum rating specified in
5)
Recommended
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
Output current on RESET pin when
driven low internally
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
INJ(RESET)
in
V
DD
Parameter
Section 12.2.2 on page
0.01µF
0.01µF
Section 12.9.1
1)
5)
1)
1)
V
h(RSTL)in
DD
4.7kΩ
4)
VSS
. Otherwise the reset will not be taken into account internally.
2)
can be ignored.
.
111.
DD
Flash versions
ROM versions
Flash versions
ROM versions
I
V
Internal reset sources
IO
V
, f
DD
DD
=+2mA
CPU
=3V
6)7)8)
R
Conditions
ON
, and T
Filter
A
unless otherwise specified.
GENERATOR
0.85xV
0.7xV
PULSE
Min
2.5
50
13
DD
DD
Section 12.2.2
Typ
2.5
0.3
200
82
30
2
WATCHDOG RESET
0.16xV
0.3xV
and the sum of I
Max
ST72324Lxx
150
72
0.7
INTERNAL
RESET
1)
DD
DD
ST72XXX
127/154
Unit
mA
kΩ
µs
µs
ns
V
V
IO
1