ST72262G2 STMicroelectronics, ST72262G2 Datasheet - Page 104
ST72262G2
Manufacturer Part Number
ST72262G2
Description
8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
Manufacturer
STMicroelectronics
Datasheet
1.ST72262G2.pdf
(172 pages)
Specifications of ST72262G2
4 K Or 8 Kbytes Program Memory
ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
4 Power Saving Modes
Halt, Active Halt,Wait and Slow
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes
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ST72260Gx, ST72262Gx, ST72264Gx
I
Acknowledge may be enabled and disabled by
software.
The I
dress can be selected by software.
The speed of the I
between Standard (up to 100KHz) and Fast I
(up to 400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 58. I
104/172
2
C BUS INTERFACE (Cont’d)
SCL or SCLI
SDA or SDAI
2
C interface address and/or general call ad-
2
C Interface Block Diagram
2
C interface may be selected
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
DATA CONTROL
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL REGISTER (CR)
2
C
The SCL frequency (F
grammable clock divider which depends on the
I
When the I
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
When the I
ports revert to being standard I/O port pins.
2
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
C bus mode.
DATA SHIFT REGISTER
DATA REGISTER (DR)
CONTROL LOGIC
COMPARATOR
INTERRUPT
2
2
C cell is disabled, the SDA and SCL
C cell is enabled, the SDA and SCL
scl
) is controlled by a pro-
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