ST7232AK1 STMicroelectronics, ST7232AK1 Datasheet - Page 78

• Manufacturer Part Number: ST7232AK1
• Description: 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST7232AK1

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232A
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 46. Generic SS Timing Diagram
Figure 47. Hardware/Software Slave Select Management
78/157
1
– SS internal must be held high continuously
MOSI/MISO
(if CPHA=0)
(if CPHA=1)
Figure
Master SS
Slave SS
Slave SS
47)
SS external pin
SSI bit
Byte 1
SSM bit
1
0
SS internal
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA=1 (data latched on 2nd clock edge):
If CPHA=0 (data latched on 1st clock edge):
Byte 2
– SS internal must be held low during the entire
– SS internal must be held low during byte
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
10.4.5.3).
46):