ST7260E2 STMicroelectronics, ST7260E2 Datasheet - Page 52

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ST7260E2

Manufacturer Part Number
ST7260E2
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7260E2

4 Or 8 Kbytes Program Memory
high density Flash (HDFlash), or FastROM with readout and write protection
Watchdog timer (WDG)
Note:
52/139
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 26. Counter timing diagram, internal clock divided by 2
Figure 27. Counter timing diagram, internal clock divided by 4
Figure 28. Counter timing diagram, internal clock divided by 8
The MCU is in reset state when the internal reset signal is high, when it is low the MCU is
running.
Timer Overflow Flag (TOF)
Timer Overflow Flag (TOF)
Timer Overflow Flag (TOF)
Counter register
Internal reset
Counter register
Counter register
Timer clock
CPU clock
Internal reset
Internal reset
Timer clock
Timer clock
CPU clock
CPU clock
FFFC
FFFC
FFFD FFFE FFFF 0000 0001 0002 0003
FFFD
FFFD
0000
0001
0000
ST7260xx

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