ST72361AR7 STMicroelectronics, ST72361AR7 Datasheet - Page 111
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ST72361AR7
Manufacturer Part Number
ST72361AR7
Description
8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, 2x LINSCI™
Manufacturer
STMicroelectronics
Datasheet
1.ST72361AR7.pdf
(225 pages)
Specifications of ST72361AR7
Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
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SERIAL PERIPHERAL INTERFACE (cont’d)
10.6.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 72. Generic SS Timing Diagram
Figure 73. Hardware/Software Slave Select Management
– SS internal must be held high continuously
Figure
(if CPHA = 0)
(if CPHA = 1)
MOSI/MISO
Master SS
Slave SS
Slave SS
73).
SS external pin
SSI bit
Byte 1
SSM bit
1
0
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA = 1 (data latched on second clock edge):
If CPHA = 0 (data latched on first clock edge):
– SS internal must be held low during the entire
– SS internal must be held low during byte
Byte 2
SS internal
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
10.6.5.3).
72):
ST72361
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