ST72361AR7 STMicroelectronics, ST72361AR7 Datasheet - Page 129
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ST72361AR7
Manufacturer Part Number
ST72361AR7
Description
8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, 2x LINSCI™
Manufacturer
STMicroelectronics
Datasheet
1.ST72361AR7.pdf
(225 pages)
Specifications of ST72361AR7
Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.7.6 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SCI.
SCI interrupts cause the device to exit from
Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited.
10.7.7 Interrupts
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
Transmit Data Register
Empty
Transmission Com-
plete
Received Data Ready
to be Read
Overrun Error or LIN
Synch Error Detected
Idle Line Detected
Parity Error
LIN Header Detection
Interrupt Event
Event
TDRE
RDRF
LHDF
Flag
IDLE
LHE
OR/
TC
PE
Control
Enable
TCIE
LHIE
ILIE
Bit
TIE
RIE
PIE
from
Wait
Exit
Yes
ST72361
129/225
from
Exit
Halt
No
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