ST7232AJ2 STMicroelectronics, ST7232AJ2 Datasheet - Page 96

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ST7232AJ2

Manufacturer Part Number
ST7232AJ2
Description
8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7232AJ2

Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, PWM and pulse generator modes
ST7232A
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.5 Low Power Modes
10.5.6 Interrupts
The SCI interrupt events are connected to the
same interrupt vector.
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
96/157
1
Mode
WAIT
HALT
In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.
Description
No effect on SCI.
SCI interrupts cause the device to exit
from Wait mode.
SCI registers are frozen.
rupt mask in the CC register is reset (RIM instruc-
tion).
Transmit Data Register
Empty
Transmission Com-
plete
Received Data Ready
to be Read
Overrun Error Detected
Idle Line Detected
Parity Error
Interrupt Event
Event
TDRE
RDRF
Flag
IDLE
OR
TC
PE
Control
Enable
TCIE
ILIE
Bit
RIE
TIE
PIE
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
from
Halt
Exit
No
No
No
No
No
No

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