ST72325J4 STMicroelectronics, ST72325J4 Datasheet - Page 193

• Manufacturer Part Number: ST72325J4
• Description: 8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72325J4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
SIM
LD A,PFDR
AND A,#$02
LD X,A
PxOR/PxDDR
LD A,#$90
LD PFDDR,A; Write into PFDDR
LD A,#$ff
LD PFOR,A
LD A,PFDR
AND A,#$02
LD Y,A
PxDDR
LD A,X
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A ; set the semaphore to '1' if edge is
detected
RIM
LD A,sema ; check the semaphore status
CP A,#$01
jrne OUT
call call_routine; call the interrupt routine
RIM
OUT:
JP while_loop
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
LD A,#$00
LD sema,A
IRET
; set the interrupt mask
; store the level before writing to
; store the level after writing to PxOR/
; check for falling edge
RIM
; entry to interrupt routine
; reset the interrupt mask
; Write to PFOR
15.1.3
interrupt routine
When an active interrupt request occurs at the
same time as the related flag is being cleared, an
unwanted reset may occur.
Note: clearing the related interrupt mask will not
generate an unwanted reset
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
– The interrupt flag is cleared within any interrupt
– The interrupt flag is cleared in any part of the
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Perform SIM and RIM operation before and after
resetting an active interrupt request.
Example:
Nested interrupt context:
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
– The interrupt flag is cleared within any interrupt
– The interrupt flag is cleared in any part of the
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
rupt routine
routine
code while this interrupt is disabled
rupt routine
routine with higher or identical priority level
code while this interrupt is disabled
SIM
reset interrupt flag
RIM
PUSH CC
SIM
reset interrupt flag
POP CC
Clearing
active
interrupts
ST72325xx
outside
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