STR912FAW44 STMicroelectronics, STR912FAW44 Datasheet
STR912FAW44
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STR912FAW44 Summary of contents
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... Doc ID 13495 Rev 6 STR91xFAxxx LQFP128 14 x 14mm LFBGA144 1.7 2 C™, 400 kHz Device summary Part number STR910FAM32, STR910FAW32, STR910FAZ32, STR912FAW32 STR911FAM42, STR911FAW42, STR912FAW42, STR912FAZ42 STR911FAM44 STR911FAW44 STR912FAW44, STR912FAZ44 STR911FAM46, STR911FAW46, STR912FAW46, STR912FAZ46 STR911FAM47, STR911FAW47, STR912FAW47, STR912FAZ47 www.st.com 1/102 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STR91xFAxxx 3.10.8 3.10.9 3.10.10 External RTC calibration clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 3.22.1 3.23 General purpose I ...
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STR91xFAxxx 7.5 LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ...
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Contents 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STR91xFAxxx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 51. 128-pin low profile quad flat package (LQFP128) mechanical data . . . . . . . . . . . . . . . . . . 96 Table 52. 144-ball low profile fine pitch ...
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STR91xFAxxx List of figures Figure 1. STR91xFA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description STR91xFA is a series of ARM-powered microcontrollers which combines a 16/32-bit ARM966E-S RISC processor core, dual-bank Flash memory, large SRAM for data or code, and a rich peripheral set to form an ideal embedded controller for a ...
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... STR91xFAxxx 2 Device summary Table 2. Device summary Part number STR910FAM32 STR910FAW32 STR910FAZ32 STR911FAM42 STR911FAM44 STR911FAM46 STR911FAM47 STR911FAW42 STR911FAW44 STR911FAW46 STR911FAW47 STR912FAW32 STR912FAW42 STR912FAW44 STR912FAW46 STR912FAW47 STR912FAZ42 STR912FAZ44 STR912FAZ46 STR912FAZ47 Flash KB RAM KB Major peripherals 256+32 64 CAN, 40 I/Os 256+32 64 CAN, EMI, 80 I/Os 256+32 64 CAN, EMI, 80 I/Os 256+32 ...
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Functional overview 3 Functional overview 3.1 System-in-a-package (SiP) The STR91xFA is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU with peripheral interfaces and analog functions, and the other die is the burst Flash. The ...
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STR91xFAxxx 3.4.2 Branch cache (BC) When instruction addresses are not sequential, such as a program branch situation, the PFQ would have to flush and reload which would cause the CPU to stall were present. Before reloading, the ...
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Functional overview Figure 1. STR91xFA block diagram VDD GND VDDQ GND VBATT 4 MHz to 25 MHz XTAL EMI Ctrl USB Bus To Ethernet PHY (MII USB not available on STR910 ** Ethernet MAC not available on STR910 ...
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STR91xFAxxx 3.5 SRAM (64 Kbytes or 96 Kbytes) A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single- cycle data accesses. As shown in Advanced High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to ...
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Functional overview 3.7 Non-volatile memories There are two independent 32-bit wide burst Flash memories enabling true read-while-write operation. The Flash memories are single-voltage erase/program with 20 year minimum data retention and 100K minimum erase cycles. The primary Flash memory is ...
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STR91xFAxxx Table 4. Sectoring of secondary Flash memory Size of secondary Flash Number of sectors Size of each sector 3.8 One-time-programmable (OTP) memory There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory calibration constants, ...
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Functional overview 3.9 Vectored interrupt controller (VIC) Interrupt management in the STR91xFA is implemented from daisy-chaining two standard ARM VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two interrupt output signals to the CPU. The ...
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STR91xFAxxx Each of 4 remaining interrupt requests generated by the wake-up unit (IRQ26 in derived from groupings of 8 interrupt sources. One group is from GPIO pins P3.2 to P3.7 plus the RTC interrupt and the USB Resume interrupt; the ...
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Functional overview Table 6. VIC IRQ channels (continued) IRQ channel VIC input hardware channel priority 25 VIC1.9 Wake-Up (all) 26 VIC1.10 Wake-up Group 0 27 VIC1.11 Wake-up Group 1 28 VIC1.12 Wake-up Group 2 29 VIC1.13 Wake-up Group 3 30 ...
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STR91xFAxxx As an option, there are a number of peripherals that do not have to receive a clock sourced from the CCU. The USB interface can receive an external clock on pin P2.7, TIM timers TIM0/ TIM1 can receive an ...
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Functional overview 3.10.5 Flash memory interface clock (FMICLK) The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at power up. The clock can be optionally divided by 2. The FMICLK determines the bus bandwidth between ...
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STR91xFAxxx 3.10.11 Operation example As an example of CCU operation MHz crystal can be connected to the main oscillator input on pins X1_CPU and X2_CPU, a 32.768 kHz crystal connected to pins X1_RTC and X2_RTC, and the clock ...
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Functional overview 3.11.2 Idle mode In this mode the CPU suspends code execution and the CPU and FMI clocks are turned off immediately after firmware sets the Idle Bit. Various peripherals continue to run based on the settings of the ...
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STR91xFAxxx 3.12.2 Battery supply An optional stand-by voltage from a battery or other source may be connected to pin VBATT to retain the contents of SRAM in the event of a loss of the main digital supplies ( ...
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... V, or 3. threshold is 2 choice of trigger level is made by STR91xFA device configuration software from STMicroelectronics or IDE from 3rd parties, and is programmed into the STR91xFA device along with other configurable items through the JTAG interface when the Flash memory is programmed. CPU firmware may prevent some LVD resets if desired by writing a control register at run- time ...
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STR91xFAxxx 3.13.7 Tamper detection On 128-pin and 144-ball STR91xFA devices only, there is a tamper detect input pin, TAMPER_IN, used to detect and record the time of a tamper event on the end product such as malicious opening of an ...
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Functional overview TAPs are daisy-chained, only one TAP will converse on the JTAG bus at any given time while the other two TAPs are in BYPASS mode. The TAP positioning order within this JTAG chain is the boundary scan TAP ...
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STR91xFAxxx 3.15.2 Boundary scan Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the majority of pins of the STR91xFA for circuit board test during manufacture of the end product. STR91xFA pins that are not serviced by boundary ...
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Functional overview 3.16 Embedded trace module (ARM ETM9, v. r2p2) The ETM9 interface provides greater visibility of instruction and data flow happening inside the CPU core by streaming compressed data at a very high rate from the STR91xFA though a ...
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STR91xFAxxx The STR91xFA MAC includes the following features: ● Supports 10 and 100 Mbps rates ● Tagged MAC frame support (VLAN support) ● Half duplex (CSMA/CD) and full duplex operation ● MAC control sublayer (control frames) support ● 32-bit CRC ...
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Functional overview 3.18.1 Packet buffer interface (PBI) The PBI manages a set of buffers inside the 2 Kbyte Packet Buffer, both for transmission and reception. The PBI will choose the proper buffer according to requests coming from the USB Serial ...
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STR91xFAxxx 3.20 UART interfaces with DMA The STR91xFA supports three independent UART serial interfaces, designated UART0, UART1, and UART2. Each interface is very similar to the industry-standard 16C550 UART device. All three UART channels support IrDA encoding/decoding, requiring only an ...
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Functional overview A single device can play the role of Master or Slave single device can be a Slave only. A Master or Slave device has the ability to suspend data transfers if the device needs more time ...
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STR91xFAxxx 3.22.1 DMA A programmable DMA channel may be assigned by CPU firmware to service each SSP channel for fast and direct transfers between the SSP bus and SRAM with little CPU involvement. Both DMA single-transfers and DMA burst-transfers are ...
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Functional overview 3.24.1 DMA A programmable DMA channel may be assigned by CPU firmware to service each ADC conversion result for fast DMA single-transfer. 3.25 Standard timers (TIM) with DMA The STR91xFA has four independent, free-running 16-bit timer/counter modules designated ...
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STR91xFAxxx 3.26 Three-phase induction motor controller (IMC) The STR91xFA provides an integrated controller for variable speed motor control applications. Six PWM outputs are generated on high current drive pins P6.0 to P6.5 for controlling a three-phase AC induction motor drive ...
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Functional overview 3.27 External memory interface (EMI) STR91xFA devices in 128-pin and 144-ball packages offer an external memory bus for connecting external parallel peripherals and memories. The EMI bus resides on ports 7, 8, and 9 and operates with either ...
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STR91xFAxxx EMI_BWR_WRLn is the data write strobe, and the output on pin EMI_RDn is the data read strobe. ● 8-bit non-multiplexed data mode bits of address are output on ports 7 and 9. The output signal on pin EMI_BWR_BWLn is ...
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Functional overview Figure 4. EMI 16-bit multiplexed connection example Figure 5. EMI 8-bit multiplexed connection example 40/102 STR91xx EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_WRHn EMI_BWR_WRLn EMI_RDn EMI_ALE P7.7 EMI_A23 P7.6 EMI_A22 P7.5 EMI_A21 P7.4 EMI_A20 P7.3 EMI_A19 P7.2 EMI_A18 P7.1 EMI_A17 ...
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STR91xFAxxx Figure 6. EMI 8-bit non-multiplexed connection example STR91xx EMI_BWR_WRLn EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_RDn P9.7 EMI_A15 P9.6 EMI_A14 P9.5 EMI_A13 P9.4 EMI_A12 P9.3 EMI_A11 P9.2 EMI_A10 P9.1 EMI_A9 P9.0 EMI_A8 P7.7 EMI_A7 P7.6 EMI_A6 P7.5 EMI_A5 P7.4 EMI_A4 P7.3 ...
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Related documentation 4 Related documentation Available from www.arm.com: ARM966E-S Rev 2 Technical Reference Manual Available from www.st.com: STR91xFA reference manual STR9 Flash programming manual (PM0020) The above is a selected list only, a full list STR91xFA application notes can be ...
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STR91xFAxxx 5 Pin description Figure 7. STR91xFAM 80-pin package pinout P4.3 P4.2 P4.1 P4.0 VSS_VSSQ VDDQ P2.0 P2.1 P5.0 VSS VDD P5.1 P6.2 P6.3 VDDQ VSSQ P5.2 P5.3 P6.0 P6 (Not Used) on STR910FAM devices. Pin 59 is ...
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Pin description Figure 8. STR91xFAW 128-pin package pinout P4.2 P4.1 P4.0 AVSS P7.0 P7.1 P7.2 VSSQ VDDQ P2.0 P2.1 P5.0 P7.3 P7.4 P7.5 VSS VDD P5.1 P6.2 P6.3 EMI_BWR_WRLn EMI_WRHn VDDQ VSSQ (3) PHYCLK_P5.2 P8.0 P5.3 P8.1 P6.0 P8.2 P6.1 ...
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STR91xFAxxx 5.1 LFBGA144 ball connections ● In Table 7 balls labelled NC are no connect balls. These NC balls are reserved for future devices and should NOT be connected to ground or any other signal. There are total of 9 ...
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Pin description 5.2 Default pin functions During and just after reset, all pins on ports 0-9 default to high-impedance input mode until CPU firmware assigns other functions to the pins. This initial input mode routes all pins on ports 0-9 ...
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STR91xFAxxx Table 8. Device pin description Package Pin Default pin name function GPIO_0. L11 P0.0 I/O GP Input, HiZ GPIO_0. K10 P0.1 I/O GP Input, HiZ GPIO_0. J11 P0.2 I/O GP Input, HiZ GPIO_0.3, ...
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Pin description Table 8. Device pin description (continued) Package Pin Default pin name function GPIO_2. P2.6 I/O GP Input, HiZ GPIO_2.7, USBCLK I/O _P2.7 GP Input, HiZ GPIO_3. P3.0 I/O GP ...
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STR91xFAxxx Table 8. Device pin description (continued) Package Pin Default pin name function GPIO_5.2, PHYCLK I/O _P5.2 GP Input, HiZ GPIO_5. P5.3 I/O GP Input, HiZ GPIO_5. J12 P5.4 I/O GP Input, ...
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Pin description Table 8. Device pin description (continued) Package Pin Default pin name function GPIO_7.7, - 119 A5 P7.7 I/O GP Input, HiZ GPIO_8. P8.0 I/O GP Input, HiZ GPIO_8. P8.1 I/O GP Input, ...
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STR91xFAxxx Table 8. Device pin description (continued) Package Pin Default pin name function EMI high byte write strobe (16-bit mode) EMI_ - Can also be WRHn configured as EMI_UBn in BGA package EMI address - 74 J10 ...
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Pin description Table 8. Device pin description (continued) Package Pin Default pin name function 68 108 E8 JTCK I JTAG clock JTAG mode 69 111 A6 JTMS I select 72 115 C6 JTDI I JTAG data in 73 117 B6 ...
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STR91xFAxxx Table 8. Device pin description (continued) Package Pin Default pin name function - 8 L2 VSSQ VSSQ VSSQ VSSQ G Digital Ground VSSQ G ...
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Memory mapping 6 Memory mapping The ARM966E-S CPU addresses a single linear address space of 4 giga-bytes (2 address 0x0000.0000 to 0xFFFF.FFFF as shown in from address 0x0000.0000, which is chip-select zero at address zero in the Flash Memory Interface ...
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STR91xFAxxx 6.3 SRAM The SRAM is aliased at three separate address ranges as shown in CPU accesses SRAM starting at 0x0400.0000, the SRAM appears on the D-TCM. When CPU access starts at 0x4000.0000, SRAM appears in the buffered AHB range. ...
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Memory mapping If the main Flash contents are incorrect, the CPU, while executing code from the secondary Flash, can download new data from any STR91xFA communication channel and program into primary Flash memory. Application code then starts after the new ...
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STR91xFAxxx Figure 9. STR91xFA memory map TOTAL 4 GB CPU MEMORY SPACE 0xFFFF.FFFF VIC0 0xFFFF.F000 RESERVED 0xFC01.0000 VIC1 0xFC00.0000 RESERVED 0x8000.0000 ENET 0x7C00.0000 8-CH DMA 0x7800.0000 EMI 0x7400.0000 USB 0x7000.0000 ENET 0x6C00.0000 8-CH DMA 0x6800.0000 EMI 0x6400.0000 USB 0x6000.0000 APB1 ...
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Electrical characteristics 7 Electrical characteristics 7.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 7.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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STR91xFAxxx Figure 11. Pin input voltage 7.2 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high static voltages. However advisable to take normal precautions to avoid application of any voltage higher ...
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Electrical characteristics Table 10. Current characteristics Symbol (1) I VDD_IO (1) I VSS_IO I IO (3) I INJ(PIN) ΣI (3) INJ(PIN) 1. The user can use GPIOs to source or sink current. In this case, the user must ensure that ...
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STR91xFAxxx 7.3 Operating conditions Table 11. Operating conditions Symbol V Digital CPU supply voltage DD V Digital I/O supply voltage DDQ SRAM backup and RTC supply (3) V BATT voltage Analog ADC supply voltage (128 pin and 144-ball ...
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Electrical characteristics 7.4 RESET_INn and power-on-reset characteristics V = 2.7 - 3.6V, V DDQ Table 13. RESET_INn and power-on-reset characteristics Symbol Parameter t RESET_INn Valid Active Low RINMIN Power-On-Reset Condition t POR duration RESET_OUT Duration t RSO (Watchdog reset) 1. ...
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STR91xFAxxx 7.5.1 LVD delay timing Case 1: When V DDQ (introduced by the VDD rising edge), a new ~10 ms delay starts before the release of RESET_OUTn. See Figure 12. LVD reset delay case 1 V (green (red) ...
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Electrical characteristics 7.6 Supply current characteristics V = 2 DDQ Table 15. Supply current characteristics Symbol Parameter I Run mode current DDRUN I Idle mode current IDLE Sleep mode I SLEEP(IDD) current, I Sleep mode I ...
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STR91xFAxxx Figure 15. Sleep mode current vs temperature with LVD on 2000 1800 1600 1400 1200 1000 800 600 400 200 -40 -20 7.6.1 Typical power consumption for frequencies below 10 MHz The following conditions apply to ● Program is ...
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Electrical characteristics 7.7 Clock and timing characteristics Table 17. Internal clock frequencies Symbol Parameter f CCU Master clock MSTR f CPU Core frequency CPUCLK f Peripheral clock for APB PCLK f Peripheral clock for AHB HCLK f Clock input OSC ...
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STR91xFAxxx 7.7.1 Main oscillator electrical characteristics V = 2 DDQ Table 18. Main oscillator electrical characteristics Symbol t Oscillator Start-up Time STUP(OSC) 1. Data characterized with quartz crystal, not tested in production. 7.7.2 X1_CPU external clock ...
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Electrical characteristics Figure 16. Typical application with an external clock source V X1H V X1L EXTERNAL CLOCK SOURCE 7.7.3 RTC clock generated from a crystal/ceramic resonator The RTC (Real-Time Clock) can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. ...
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STR91xFAxxx Table 21. RTC crystal electrical characteristics Symbol f Resonant frequency O R Series resistance S C Load capacitance L Figure 17. Typical application with a 32.768 kHz crystal RESONATOR WITH INTEGRATED CAPACITORS 7.7.4 PLL electrical ...
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Electrical characteristics 7.8 Memory characteristics 7.8.1 SRAM characteristics Table 23. SRAM and hardware registers Symbol Parameter V Supply voltage for data retention DR 1. Guaranteed by characterization, not tested in production. 7.8.2 Flash memory characteristics V = 2.7 - 3.6 ...
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STR91xFAxxx Table 25. Flash memory program/erase characteristics (Flash size = MB) Parameter Primary bank (2 Mbytes) Bank erase Primary bank (1 Mbytes) Secondary bank (128 Kbytes) Of primary bank (64 Kbytes) Sector erase Of secondary bank ...
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Electrical characteristics 7.9 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 7.9.1 Functional EMS (electro magnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is ...
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STR91xFAxxx 7.9.2 Electro magnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE ...
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... Symbol LU Static latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 74/102 Parameter = +25 ° ...
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STR91xFAxxx 7.10 I/O characteristics V = 2 DDQ Table 31. I/O characteristics Symbol Parameter V Input high level IH V Input low level IL Input hysteresis V HYS Schmitt trigger Output high level High current pins ...
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Electrical characteristics 7.11 External memory bus timings V = 2 DDQ Table 32. EMI bus clock period Symbol t BCLK 1. The internal EMI Bus clock signal is available externally only on LFBGA144 packages (ball M8), ...
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STR91xFAxxx Non-mux read Figure 19. Non-mux bus read timings EMI_CSxn EMI_A [15:0] EMI_D[7:0] EMI_RDn Table 34. EMI read operation Symbol Parameter Read to CSn t RCR inactive Read address t RAS setup time Read data setup t RDS time Read ...
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Electrical characteristics Mux write Figure 20. Mux write diagram EMI_CSxn EMI_A LE EMI_A [23:16] EMI_A D[15:0] EMI_WRLn EMI_WRHn Table 35. Mux write times Symbol Parameter WRn to CSn t WCR inactive Write address t WAS setup time Write data setup ...
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STR91xFAxxx Mux read Figure 21. Mux read diagram EMI_CSxn EMI_A LE EMI_A [23:16] EMI_A D[15:0] EMI_RDn Table 36. Mux read times Symbol Parameter Read to CSn t RCR inactive Read address setup t RAS time Read data setup t RDS ...
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Electrical characteristics Page mode read Figure 22. Page mode read diagram CSx EMI_RD A15-A2 A15-A2 A1-A0 D0-D7 Table 37. Page mode read times Symbol Parameter t Read data hold time RDH t Read data setup time RDS t ALE pulse ...
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STR91xFAxxx 7.11.2 Synchronous mode Sync burst write Figure 23. Sync burst write diagram EMI_BCLK EMI_ALE CS EMI_WE EMI_UB EMI_LBN EMI_BAA EMI_WAIT AD15:0 D_OUT15:0 EMI_BCLK EMI_ALE CS EMI_WE EMI_BAA A[15:0] D_IN[15:0] EMI_WAIT A15:0 Data Doc ID ...
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Electrical characteristics Table 38. Sync burst write times Symbol t D1BAA t D2BAA t D1ALE t D2ALE t D1WR t D2WR t D1A t D2A t D1CS t D2CS 82/102 Parameter BAA t D1 ...
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STR91xFAxxx Sync burst read Figure 24. Sync burst read diagram EMI_BCLK EMI_ALE CSxn EMI_RDn EMI_BAAn A[15:0] D_IN[15:0] EMI_WAITn Table 39. Sync burst read times Symbol t D1BAA t D2BAA t D1ALE t D2ALE t D1RD t D2RD t D1A t ...
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Electrical characteristics 7.12 Communication interface electrical characteristics 7.12.1 10/100 Ethernet MAC electrical characteristics V = 2 DDQ Ethernet MII interface timings Figure 25. MII_RX_CLK and MII_TX_CLK timing diagram MII_RX_TCLK, MII_TX_CLK Table 40. MII_RX_CLK and MII_TX_CLK timing ...
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STR91xFAxxx Ethernet MII management timings Figure 27. Ethernet MII management timing diagram MDC MDIO output MDIO input Table 42. Ethernet MII management timing table Symbol MDIO delay from rising 1 edge of MDC MDIO setup time to rising 2 edge ...
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Electrical characteristics Table 43. Ethernet MII transmit timing table Symbol MII_TX_CLK high to 1 MII_TX_EN valid MII_TX_CLK high to 2 MII_TX_EN invalid MII_CRS valid to 3 MII_TX_CLK high MII_TX_CLK high to 4 MII_CRS invalid MII_COL valid to 5 MII_TX_CLK high ...
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STR91xFAxxx 2 7.12 electrical characteristics V = 2 DDQ 2 Table 45 electrical characteristics Symbol Bus free time between a STOP t BUF and START condition Hold time START condition. t After ...
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Electrical characteristics 7.12.5 SPI electrical characteristics V = 2 DDQ Table 46. SPI electrical characteristics Symbol f SCLK SPI clock frequency 1/t c(SCLK) t r(SCLK) SPI clock rise and fall times 50pF load t f(SCLK) t ...
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STR91xFAxxx Figure 31. SPI slave timing diagram with CPHA = 1 NSS INPUT t su( NSS ) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t a(SO) MISO OUTPUT MOSI INPUT Figure 32. SPI master timing diagram NSS INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 ...
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Electrical characteristics 7.13 ADC electrical characteristics V = 2 DDQ Table 47. General ADC electrical characteristics Symbol Parameter V Input voltage range AIN RES Resolution N Number of input channels CH f ADC clock frequency ADC ...
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STR91xFAxxx Table 48. ADC conversion time (silicon Rev G) Symbol Parameter t Single mode conversion time CONV(S] TR(S) Single mode throughput rate t Continuous mode conversion time CONV(C] TR(C) Continuous mode throughput rate 1. Guaranteed by design, not tested in ...
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Electrical characteristics Figure 33. ADC conversion characteristics Digital Result 1023 1022 1021 Legend: (1) Example of an actual transfer curve (2) The ideal transfer curve (3) ...
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STR91xFAxxx 8 Device marking 8.1 STR91xFAx32 / STR91xFAx42 / STR91xFAx44 Figure 34. Device marking for revision G LQFP80 and LQFP128 packages Figure 36. Device marking for revision H LQFP80 and LQFP128 packages Figure 35. Device marking for revision G LFBGA144 ...
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Device marking 8.2 STR91xFAx46 / STR91xFAx47 Figure 38. Device marking for revision A LQFP80 and LQFP128 packages A 94/102 Figure 39. Device marking for revision A LFBGA144 packages Doc ID 13495 Rev 6 STR91xFAxxx A ...
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STR91xFAxxx 9 Package mechanical data Figure 40. 80-pin low profile quad flat package (LQFP80) outline SEATING PLANE C Table 50. 80-pin low profile quad flat package (LQFP80) mechanical data Dim. Min A A1 0.05 A2 1.35 b 0.17 c 0.09 ...
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Package mechanical data Figure 41. 128-pin low profile quad flat package (LQFP128) outline SEATING PLANE C Table 51. 128-pin low profile quad flat package (LQFP128) mechanical data Dim. Min A A1 0.05 A2 1.35 b 0.13 c 0.09 D 15.80 ...
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STR91xFAxxx Figure 42. 144-ball low profile fine pitch ball grid array package (LFBGA144) outline Table 52. 144-ball low profile fine pitch ball grid array package (LFBGA144) mechanical data Dim. Min A 1. 0.35 D 9.85 D1 ...
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Package mechanical data Figure 43. Recommended PCB design rules (0.80/0.75 mm pitch BGA) 9.1 ECOPACK To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions, ...
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STR91xFAxxx Table 53. Thermal characteristics Symbol Thermal resistance junction-ambient Θ JA LQFP 0.5 mm pitch Thermal resistance junction-ambient Θ JA LQFP128 - 0.4 mm pitch Thermal resistance junction-ambient ...
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Ordering information 10 Ordering information Table 54. Ordering information scheme Example: Family ARM9 microcontroller family Series 1 = STR9 series 1 Feature set 0 = CAN, UART, IrDA, I2C, SSP 1 = USB, CAN, UART, IrDA, I2C, SSP 2 = ...
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STR91xFAxxx 11 Revision history Table 55. Document revision history Date 09-May-2007 26-Nov-2007 14-May-2008 17-Jul-2008 22-Dec-2008 02-Jul-2009 Revision 1 Initial release Updated Standby current in characteristics on page 64 Added Section 7.1: Parameter conditions on page 58 Added Section 7.7.2: X1_CPU ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...