STR912FAW44 STMicroelectronics, STR912FAW44 Datasheet - Page 26

• Manufacturer Part Number: STR912FAW44
• Description: ARM966E-S 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR912FAW44

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

Functional overview
3.13.2
3.13.3
3.13.4
3.13.5
3.13.6
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Supply voltage dropout
LVD circuitry will always cause a global reset if the CPU’s V
threshold of 1.4 V.
However, the LVD trigger threshold to cause a global reset for the I/O ring’s V
set to one of two different levels, depending if V
3.3 V, or 3.0V to 3.6 V. If V
threshold is 2.4 V. If V
choice of trigger level is made by STR91xFA device configuration software from
STMicroelectronics or IDE from 3rd parties, and is programmed into the STR91xFA device
along with other configurable items through the JTAG interface when the Flash memory is
programmed.
CPU firmware may prevent some LVD resets if desired by writing a control register at run-
time. Firmware may also disable the LVD completely for lowest-power operation when an
external LVD device is being used.
Watchdog timer
The STR91xFA has a 16-bit down-counter (not one of the four TIM timers) that can be used
as a watchdog timer or as a general purpose free-running timer/counter. The clock source is
the peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled
by firmware as a watchdog, this timer will cause a system reset if firmware fails to
periodically reload this timer before the terminal count of 0x0000 occurs, ensuring firmware
sanity. The watchdog function is off by default after a reset and must be enabled by
firmware.
External RESET_INn pin
This input signal is active-low with hystereses (V
reset signals on the circuit board (such as closure to ground from a push-button) may be
connected directly to the RESET_INn pin, but an external pull-up resistor to V
present as there is no internal pullup on the RESET_INn pin.
A valid active-low input signal of t
reset within the STR91xFA. There is also a RESET_OUTn pin on the STR91xFA that can
drive other system components on the circuit board. RESET_OUTn is active-low and has
the same timing of the Power-On-Reset (POR) shown next, t
Power-up
The LVD circuitry will always generate a global reset when the STR91xFA powers up,
meaning internal reset is active until V
POR condition has a duration of t
address 0x0000.0000 in Flash memory. It is not possible for the CPU to boot from any other
source other than Flash memory.
JTAG debug command
When the STR91xFA is in JTAG debug mode, an external device which controls the JTAG
interface can command a system reset to the STR91xFA over the JTAG channel.
DDQ
DDQ
operation is 3.0 V and 3.6 V, the LVD threshold is 2.7 V. The
Doc ID 13495 Rev 6
operation is at 2.7 V to 3.3 V, the LVD dropout trigger
RINMIN
POR
, after which the CPU will fetch its first instruction from
DDQ
duration on the RESET_INn pin will cause a system
and V
DDQ
DD
HYS
are both above the LVD thresholds. This
will be operated in the range of 2.7 V to
). Other open-drain, active-low system
DD
POR
source drops below it’s fixed
.
STR91xFAxxx
DDQ
DDQ
source is
must be