STR912FAW44 STMicroelectronics, STR912FAW44 Datasheet - Page 55

• Manufacturer Part Number: STR912FAW44
• Description: ARM966E-S 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR912FAW44

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

STR91xFAxxx
6.3
6.4
6.4.1
6.4.2
SRAM
The SRAM is aliased at three separate address ranges as shown in
CPU accesses SRAM starting at 0x0400.0000, the SRAM appears on the D-TCM. When
CPU access starts at 0x4000.0000, SRAM appears in the buffered AHB range. Beginning at
CPU address 0x5000.0000, SRAM is in non-buffered AHB range. The SRAM size must be
specified by CPU intitialization firmware writing to a control register after any reset condition.
Default SRAM size is 32K bytes, with option to set to 64K bytes on STR91xFAx3x devices,
and to 96K bytes on STR91xFAx4x devices.
When other AHB bus masters (such as a DMA controller) write to SRAM, their access is
never buffered. Only the CPU can make use of buffered AHB writes.
Two independent Flash memories
The STR91xFA has two independent Flash memories, the larger primary Flash and the
small secondary Flash. It is possible for the CPU to erase/write to one of these Flash
memories while simultaneously reading from the other.
One or the other of these two Flash memories may reside at the “boot” address position of
0x0000.0000 at power-up or at reset as shown in
the first sector of primary Flash memory is enabled and residing at the boot position, and the
secondary Flash memory is disabled. This default condition may be optionally changed as
described below.
Default configuration
When the primary Flash resides at boot position, typical CPU initialization firmware would
set the start address and size of the main Flash memory, and go on to enable the secondary
Flash, define it’s start address and size. Most commonly, firmware would place the
secondary Flash start address at the location just after the end of the primary Flash
memory. In this case, the primary Flash is used for code storage, and the smaller secondary
Flash can be used for data storage (EEPROM emulation).
Optional configuration
Using the STR91xFA device configuration software tool, or IDE from 3rd party, one can
specify that the smaller secondary Flash memory is at the boot location at reset and the
primary Flash is disabled. The selection of which Flash memory is at the boot location is
programmed in a non-volatile Flash-based configuration bit during JTAG ISP. The boot
selection choice will remain as the default until the bit is erased and re-written by the JTAG
interface. The CPU cannot change this choice for boot Flash, only the JTAG interface has
access.
In this case where the secondary Flash defaults to the boot location upon reset, CPU
firmware would typically initialize the Flash memories the following way. The secondary
Flash start address and size is specified, then the primary Flash is enabled and its start
address and size is specified. The primary Flash start address would typically be located
just after the final address location of the secondary Flash. This configuration is particularly
well-suited for In-Application-Programming (IAP). The CPU would boot from the secondary
Flash memory, initialize the system, then check the contents of the primary Flash memory
(by checksum or other means). If the contents of primary Flash is OK, then CPU execution
continues from either Flash memory.
Doc ID 13495 Rev 6
Figure
9. The default configuration is that
Figure
Memory mapping
9. When the
55/102