ST72561AR7 STMicroelectronics, ST72561AR7 Datasheet - Page 243

• Manufacturer Part Number: ST72561AR7
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72561AR7

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

12.12 COMMUNICATION INTERFACE CHARACTERISTICS
12.12.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 138. SPI Slave Timing Diagram with CPHA = 0
Notes:
1. Data based on design simulation and/or characterization results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3 x V
4. Depends on f
OSC
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCK
r(SCK)
f(SCK)
su(SS)
h(SS)
w(SCKH)
su(MI)
su(SI)
h(MI)
a(SO)
dis(SO)
v(SO)
h(SO)
v(MO)
h(MO)
w(SCKL)
h(SI)
MISO
MOSI
Symbol
, and T
1)
= 1 / t
1)
1)
1)
1)
1)
1)
1)
1)
1)
SS
1)
1)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
OUTPUT
INPUT
1)
1)
INPUT
c(SCK)
A
unless otherwise specified.
CPU
See note 2
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
. For example, if f
t
a(SO)
t
su(SS)
t
su(SI)
Parameter
4)
CPU
MSB IN
t
t
w(SCKH)
w(SCKL)
MSB OUT
= 8 MHz, then T
t
t
h(SI)
c(SCK)
Master, f
Slave, f
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
t
v(SO)
DD
CPU
,
Conditions
BIT6 OUT
CPU
DD
CPU
= 8 MHz
and 0.7 x V
= 8 MHz
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
= 1 / f
3)
CPU
BIT1 IN
DD
= 125ns and t
t
h(SO)
.
f
CPU
(4 x T
t
t
/ 128 = 0.0625 f
r(SCK)
f(SCK)
See I/O port pin description
su(SS)
Min
CPU
120
100
100
90
0
0
0
0
LSB IN
) + 50
LSB OUT
= 550ns.
t
h(SS)
f
CPU
CPU
Max
120
240
120
90
/ 4 = 2
/ 2 = 4
t
ST72561
dis(SO)
243/265
See
note 2
MHz
Unit
ns