ST72324LS4 STMicroelectronics, ST72324LS4 Datasheet - Page 124

• Manufacturer Part Number: ST72324LS4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72324LS4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Lxx
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for V
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. I
respected, the injection current must be limited externally to the I
while a negative injection is induced by V
corresponding V
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see
based on design simulation and technology characteristics, not tested in production. This value depends on V
perature values.
5. The R
scribed in
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 65. Connecting Unused I/O Pins
124/154
1
ΣI
I
Symbol
INJ(PIN)
t
t
INJ(PIN)
t
f(IO)out
r(IO)out
w(IT)in
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
INJ(PIN)
greater EMC robustness and lower cost.
V
R
C
V
V
I
lkg
I
hys
PU
S
IH
IO
IL
3)
PU
3)
Figure
must never be exceeded. This is implicitly insured if V
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Injected Current on flash device pin
PB0
Injected Current on other I/O pins
Total injected current (sum of all I/O
and control pins)
Input leakage current
Static current consumption
Weak pull-up equivalent resistor
I/O pin capacitance
Output high to low level fall time
Output low to high level rise time
External interrupt pulse time
pull-up equivalent resistor is based on a resistive transistor (corresponding I
IN
66).
maximum must always be respected
V
DD
Parameter
10kΩ
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
1)
1)
ST72XXX
IN
6)
ST72XXX
<V
1)
5)
SS
1)
2)
. For true open-drain pads, there is no positive injection current, and the
V
V
Floating input mode
V
C
Between 10% and 90%
DD
DD
SS
IN
L
=50pF
=
=3V
, f
≤
V
SS
OSC
V
Conditions
Figure
IN
≤
, and T
V
Figure 66. Typical I
V
DD
65). Static peak current value taken at a fixed V
INJ(PIN)
DD
IN
=3V
maximum is respected. If V
A
4)
unless otherwise specified.
value. A positive injection is induced by V
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0
2
2 .5
0.7xV
Min
110
0
1
T a = 1 4 0 ° C
T a = 9 5 ° C
T a = 2 5 ° C
T a = -4 5 ° C
3
DD
PU
3 .5
V d d (V )
vs. V
PU
4
Typ
180
0.8
25
25
5
current characteristics de-
4 .5
DD
IN
5
maximum cannot be
with V
0.3xV
5 .5
± 25
Max
200
250
± 4
+4
±1
DD
6
IN
DD
=V
and tem-
IN
SS
IN
t
Unit
mA
mA
CPU
µA
kΩ
pF
value,
ns
V
V
>V
DD