ST7MC2R6 STMicroelectronics, ST7MC2R6 Datasheet - Page 135
ST7MC2R6
Manufacturer Part Number
ST7MC2R6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2R6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN PRESCALER FRACTION REGISTER
(LPFR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:4 = Reserved.
Bits 3:0 = LPFR[3:0] Fraction of LDIV
These 4 bits define the fraction of the LIN Divider
(LDIV):
1. When initializing LDIV, the LPFR register must
be written first. Then, the write to the LPR register
7
0
LPFR[3:0]
Eh
Fh
0h
1h
...
0
0
0
Fraction (LDIV)
LPFR
3
14/16
15/16
1/16
...
0
LPFR
2
LPFR
1
LPFR
0
0
will effectively update LDIV and so the clock gen-
eration.
2. In LIN Slave mode, if the LPR[7:0] register is
Examples of LDIV coding:
Example 1: LPR = 27d and LPFR = 12d
This leads to:
Mantissa (LDIV) = 27d
Fraction (LDIV) = 12/16 = 0.75d
Therefore LDIV = 27.75d
Example 2: LDIV = 25.62d
This leads to:
LPFR = rounded(16*0.62d)
= rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh
Example 3: LDIV = 25.99d
This leads to:
LPFR = rounded(16*0.99d)
= rounded(15.84d) = 16d
equal to 00h, the transceiver and receiver input
clocks are switched off.
ST7MC1xx/ST7MC2xx
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