ST72325S6 STMicroelectronics, ST72325S6 Datasheet - Page 125

• Manufacturer Part Number: ST72325S6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72325S6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

I
10.7.5 Low Power Modes
10.7.6 Interrupts
Figure 70. Event Flags and Interrupt Generation
Note: The I
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
2
WAIT
HALT
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
C BUS INTERFACE (Cont’d)
Mode
*
EVF can also be set by EV6 or an error from the SR2 register.
STOPF
ADD10
BERR
ARLO
ADSL
*
BTF
No effect on I
I
I
In HALT mode, the I
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
2
2
SB
AF
2
C interrupts cause the device to exit from WAIT mode.
C registers are frozen.
C interrupt events are connected to
2
C interface.
Interrupt Event
2
C interface is inactive and does not acknowledge data on the bus. The I
ITE
Description
ADSEL
STOPF
ADD10
BERR
Event
ARLO
Flag
BTF
SB
AF
Control
Enable
ITE
Bit
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ST72325xx
2
C interface
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from
Halt
Exit
No
No
No
No
No
No
No
No