ST7263BE2 STMicroelectronics, ST7263BE2 Datasheet - Page 110

• Manufacturer Part Number: ST7263BE2
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BE2

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

On-chip peripherals
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Mode selection
The interface can operate in the four following modes:
●
●
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition and from master to slave in case of arbitration loss or a STOP generation, allowing
then Multi-Master capability.
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the
start condition is the address byte; it is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to
Figure 46. I²C bus protocol
Acknowledge may be enabled and disabled by software.
The I²C interface address and/or general call address can be selected by software.
The speed of the I²C interface may be selected between Standard (up to 100 kHz) and Fast
I²C (up to 400 kHz).
SDA/SCL line control
Transmitter mode: the interface holds the clock line low before transmission to wait for the
microcontroller to write the byte in the Data register.
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data register.
The SCL frequency (F
the I²C bus mode.
When the I²C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
Slave transmitter/receiver
Master transmitter/receiver
SCL
SDA
CONDITION
START
SCL
MSB
) is controlled by a programmable clock divider which depends on
1
Doc ID 7516 Rev 8
2
8
Figure
ACK
9
46.
CONDITION
STOP
VR02119B
ST7263Bxx