ST72321J7-Auto STMicroelectronics, ST72321J7-Auto Datasheet - Page 101

• Manufacturer Part Number: ST72321J7-Auto
• Description: 8-bit MCU for automotive with 48 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321J7-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
Note:
16-bit read sequence
The 16-bit read sequence (from either the Counter Register or the Alternate Counter
Register) is illustrated in
Figure 42. 16-bit read sequence
The user must read the MS Byte first; the LS Byte value is then buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever timer mode is used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h, after which
●
●
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1.
2.
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a Reset).
the TOF bit of the SR register is set
a timer interrupt is generated if
–
–
Reading the SR register while the TOF bit is set
An access (read or write) to the CLR register
the TOIE bit of the CR1 register is set and
the I bit of the CC register is cleared
Beginning of the sequence
At t0
At t0 +Dt
Sequence completed
Figure
Doc ID 13829 Rev 1
42.
instructions
Read
MS Byte
Read
LS Byte
Other
Returns the buffered
LS Byte value at t0
LS Byte
is buffered
16-bit timer
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