ST72260G1 STMicroelectronics, ST72260G1 Datasheet - Page 139

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ST72260G1

Manufacturer Part Number
ST72260G1
Description
8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72260G1

4 K Or 8 Kbytes Program Memory
ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
4 Power Saving Modes
Halt, Active Halt,Wait and Slow
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes
CLOCK CHARACTERISTICS (Cont’d)
13.5.5 PLL Characteristics
Note:
1. Data characterized but not tested.
Figure 74. PLL Jitter vs. Signal frequency
Note 1: Measurement conditions: f
V
f
∆ f
OSC
DD(PLL)
Symbol
CPU
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
/f
CPU
2000
PLL Operating Range
PLL input frequency range
Instantaneous PLL jitter
Application Signal Frequency (KHz)
1000
Parameter
500
250
CPU
1)
PLL ON
PLL OFF
= 4MHz, T
125
T
T
f
f
OSC
OSC
A
A
1
0 to 70
-40 to +85
= 4 MHz.
= 2 MHz.
A
Conditions
= 25°C
°C
°C
The user must take the PLL jitter into account in
the application (for example in serial communica-
tion or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore the longer the
period of the application signal, the less it will be
impacted by the PLL jitter.
Figure 74
cation signals in the range 125kHz to 2MHz. At fre-
quencies of less than 125KHz, the jitter is negligi-
ble.
ST72260Gx, ST72262Gx, ST72264Gx
shows the PLL jitter integrated on appli-
Min
3.5
4.5
2
Typ
1.0
2.5
Max
5.5
5.5
2.5
4.0
4
139/172
MHz
Unit
%
%
V

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