ST72321AR7 STMicroelectronics, ST72321AR7 Datasheet - Page 43

• Manufacturer Part Number: ST72321AR7
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321AR7

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see
10.2 on page 57
register).
The MCU can exit ACTIVE-HALT mode on recep-
tion of an MCC/RTC interrupt or a RESET. When
exiting ACTIVE-HALT mode by means of an inter-
rupt, no 256 or 4096 CPU cycle delay occurs. The
CPU resumes operation by servicing the interrupt
or by fetching the reset vector which woke it up
(see
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION: When exiting ACTIVE-HALT mode fol-
lowing an MCC/RTC interrupt, OIE bit of MCCSR
register must not be cleared before t
the interrupt occurs (t
MCCSR
OIE bit
0
1
Figure
HALT mode
ACTIVE-HALT mode
Power Saving Mode entered when HALT
27).
for more details on the MCCSR
instruction is executed
DELAY
= 256 or 4096 t
DELAY
CPU
section
after
de-
lay depending on option byte). Otherwise, the ST7
enters HALT mode for the remaining t
od.
Figure 26. ACTIVE-HALT Timing Overview
Figure 27. ACTIVE-HALT Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
4. Only the MCC/RTC interrupt can exit the MCU
from ACTIVE-HALT mode.
[MCCSR.OIE=1]
INSTRUCTION
RUN
HALT INSTRUCTION
N
(MCCSR.OIE=1)
HALT
ST72321Rx ST72321ARx ST72321Jx
ACTIVE
INTERRUPT
HALT
Y
256 OR 4096 CPU
CYCLE DELAY
4)
INTERRUPT
RESET
OR
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
FETCH RESET VECTOR
N
CYCLE DELAY
RESET
Y
1)
VECTOR
FETCH
2)
DELAY
RUN
XX
XX
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
3)
3)
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