DS2431 Maxim, DS2431 Datasheet - Page 20

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DS2431

Manufacturer Part Number
DS2431
Description
The DS2431 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each
Manufacturer
Maxim
Datasheet

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1024-Bit, 1-Wire EEPROM
by the bus master. The DS2431 transmits this CRC only
if E[2:0] = 111b.
With the Read Scratchpad command, the CRC is gen-
erated by first clearing the CRC generator and then
shifting in the command code, the target addresses
Figure 13. CRC-16 Hardware Description and Polynomial
20
<8–T[2:0] bytes>
X
<Data to EOM>
______________________________________________________________________________________
8
Programming
X
0
SYMBOL
AA Loop
FF Loop
CRC-16
STAGE
TA-E/S
Select
9TH
CPS
RST
STAGE
WS
RM
PD
RS
TA
1ST
X
9
X
1
STAGE
10TH
Command-Specific 1-Wire Communication Protocol—Legend
STAGE
2ND
1-Wire reset pulse generated by master.
1-Wire presence pulse generated by slave.
Command and data to satisfy the ROM function protocol.
Command "Write Scratchpad."
Command "Read Scratchpad."
Command "Copy Scratchpad."
Command "Read Memory."
Target address TA1, TA2.
Target address TA1, TA2 with E/S byte.
Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address.
Transfer of as many data bytes as are needed to reach the end of the memory.
Transfer of an inverted CRC-16.
Indefinite loop where the master reads FF bytes.
Indefinite loop where the master reads AA bytes.
Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.
X
10
STAGE
11TH
X
11
X
2
STAGE
12TH
STAGE
3RD
X
POLYNOMIAL = X
12
X
3
STAGE
13TH
STAGE
4TH
X
13
16
X
+ X
4
STAGE
14TH
15
TA1 and TA2, the E/S byte, and the scratchpad data as
they were sent by the DS2431. The DS2431 transmits
this CRC only if the reading continues through the end
of the scratchpad. For more information on generating
CRC values, refer to Application Note 27.
STAGE
+ X
5TH
DESCRIPTION
2
+ 1
X
14
X
5
STAGE
15TH
STAGE
6TH
X
6
STAGE
7TH
X
15
X
INPUT DATA
7
STAGE
16TH
STAGE
8TH
X
16
CRC OUTPUT

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