71M6531D Maxim, 71M6531D Datasheet - Page 61
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71M6531D
Manufacturer Part Number
71M6531D
Description
The 71M6531D/F and 71M6532D/F are highly integrated SoC devices with an MPU core, RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6531D.pdf
(120 pages)
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and within three crystal cycles, the MPU begins to execute. The MPU can determine whether the timer
woke it by checking the AUTOWAKE interrupt flag (IE_WAKE).
WAKE_PRD[2:0] and WAKE_RES. WAKE_RES selects a timer LSB of either 1 minute (WAKE_RES = 1) or
2.5 seconds (WAKE_RES = 0). WAKE_PRD[2:0] selects a duration of from 1 to 7 LSBs.
LCD_ONLY is initiated. Setting WAKE_ARM presets the timer with the values in WAKE_RES and WAKE_PRD
and readies the timer to start when the processor writes to SLEEP or LCD_ONLY. The timer is reset and
disarmed whenever the processor is awake. Thus, if it is desired to wake the MPU periodically (every 5
seconds, for example) the timer must be rearmed every time the MPU is awakened.
four-quadrant metering. These measurements are then accessed by the MPU, processed further and
output using the peripheral devices available to the MPU.
Figure
FDS 6531/6532 005
2.5
As described above, the part will always wake up in MISSION mode when system power is restored.
Additionally, the part will wake up in BROWNOUT mode when PB rises (push button is pressed) or when
a timeout of the wake-up timer occurs.
2.5.1
If the part is in SLEEP or LCD mode, it can be awakened by a rising edge on the PB pin. This pin is normally
pulled to GND and can be pulled high by a push button depression. Before the PB signal rises, the MPU
is in reset due to WAKE being low. When PB rises, WAKE rises and within three crystal cycles, the MPU
begins to execute. The MPU can determine whether the PB signal woke it up by checking the IE_PB flag.
Figure 25
will reject between 31 ms and 62 ms of noise. Detection hardware will ignore all transitions after the initial
rising edge. This will continue until the MPU clears the IE_PB bit.
2.5.2
If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer. Until this timer times out,
the MPU is in reset due to WAKE being low. When the wake-up timer times out, the WAKE signal rises
2.6
The data flow between the Compute Engine (CE) and the MPU is shown in
Figure
application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA, IB
and VB, performing calculations to measure active power (Wh), reactive power (VARh), A
v1.3
For debouncing, the PB pin is monitored by a state machine operating from a 32 Hz clock. This circuit
The wake-up timer begins timing when the part enters LCD or SLEEP mode. Its duration is controlled by
The timer is armed by WAKE_ARM = 1. It must be armed at least three RTC cycles before SLEEP or
26 illustrates the CE/MPU data flow.
26. In a typical
Wake-Up Behavior
Wake on PB
Wake on Timer
Data Flow
shows the Wake Up timing.
(V3P3SYS)
MPU Mode
PB or wake-
PLL_OK
System
WAKE
Power
up timer
© 2005-2010 TERIDIAN Semiconductor Corporation
LCD
Figure 25: Wake Up Timing
15 CK32
cycles
BROWNOUT
Data Sheet 71M6531D/F-71M6532D/F
time
2
h and V
2
h for
61
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