71M6531D Maxim, 71M6531D Datasheet - Page 83

• Manufacturer Part Number: 71M6531D
• Description: The 71M6531D/F and 71M6532D/F are highly integrated SoC devices with an MPU core, RTC, flash, and LCD driver
• Manufacturer: Maxim

FDS 6531/6532 005
v1.3
LCD_SEG33[3:0]
…
LCD_SEG35[3:0]
LCD_SEG37[3:0] 2055[3:0]
LCD_SEG39[3:0]
…
LCD_SEG41[3:0]
LCD_SEG48[7:4]
…
LCD_SEG49[7:4]
LCD_SEG63[7:4]
…
LCD_SEG66[7:4]
LCD_SEG71[7:4]
…
LCD_SEG73[7:4]
LCD_Y
M26MHZ
M40MHZ
MPU_DIV[2:0]
Name
2051[3:0]
…
2053[3:0]
2057[3:0]
…
2059[3:0]
2036[7:4]
…
2037[7:4]
2045[7:4]
…
2048[7:4]
204D[7:4]
…
204F[7:4]
2021[6]
2005[4]
2005[0]
2004[2:0]
Location
Reset
…
…
…
…
…
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake
…
…
…
…
…
L
L
L
L
L
L
L
L
L
L
L
L
0
0
0
© 2005-2010 TERIDIAN Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dir
…
…
…
…
…
LCD Blink Frequency (ignored if blink is disabled or if the segment is off).
M26MHZ and M40MHZ set the master clock (MCK) frequency. These bits are reset on
chip reset and may only be set. Attempts to write zeroes to M40MHZ and M26MHZ.are
ignored.
The MPU clock divider (from MCK). These bits may be programmed by MPU without
risk of losing control.
MPU_DIV[2:0]
0 = 1 Hz (500 ms ON, 500 ms OFF)
1 = 0.5 Hz (1 s ON, 1 s OFF)
000
001
010
011
100
101
110
111
Resulting Clock Frequency
MCK/2
MCK/2
MCK/2
MCK/2
MCK/2
MCK/2
MCK/2
MCK/2
2
3
4
5
6
7
8
8
Description
Data Sheet 71M6531D/F-71M6532D/F
83