71M6531D Maxim, 71M6531D Datasheet - Page 68
71M6531D
Manufacturer Part Number
71M6531D
Description
The 71M6531D/F and 71M6532D/F are highly integrated SoC devices with an MPU core, RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6531D.pdf
(120 pages)
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and OPT_RXINV, respectively.
available in BROWNOUT mode. The OPT_TXMOD bit enables modulation. The duty cycle is controlled
by OPT_FDC[1:0], which can select 50%, 25%, 12.5% and 6.25% duty cycle. A 6.25% duty cycle means
OPT_TX is low for 6.25% of the period. The OPT_RX pin uses digital signal thresholds. It may need an
analog filter when receiving modulated optical signals.
If operation in BROWNOUT mode is desired, the external components should be connected to V3P3D.
The amount of hysteresis depends on the choice of R1 and R3: If V1 < VBIAS, approximately 1 µA will
flow into the on-chip V1 comparator causing a voltage drop. If V1 ≥ VBIAS, almost no current will flow
into the comparator. The voltage drop will require V3P3 to be slightly higher for V1 to cross the VBIAS
threshold when V3P3 is rising as compared to when V3P3 is falling. Maintaining sufficient hysteresis
helps to eliminate rapid mode changes which may occur in cases where the power supply is unstable with
V1 close to the VBIAS threshold point.
Data Sheet 71M6531D/F-71M6532D/F
The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV
3.10
A voltage divider should be used to establish that V1 is in a safe range when the meter is in MISSION
mode (see
timer enabled. The resistor divider ratio must be chosen so that V1 crosses the VBIAS threshold when
V3P3 is near the minimum supply voltage (3.0 VDC). A series resistor (R3) provides additional hysteresis,
and a capacitor to ground (C1) is added for enhanced EMC immunity.
68
The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not
With modulation, an optical emitter can be operated at higher current than nominal, enabling it to
increase the distance along the optical path.
Connecting the V1 Pin
Figure
37). V1 must be lower than 2.9 V in all cases in order to keep the hardware watchdog
71M6531D/F or 71M6532D/F
GND
V3P3
© 2005-2010 TERIDIAN Semiconductor Corporation
Figure 36: Connection for Optical Components
OPT_RX
OPT_TX
Figure 37: Voltage Divider for V1
16.9kΩ
100 pF
R
1
R
2
10 kΩ
R
20kΩ
2
R
V3P3SYS
R
LED
3
100pF
Phototransistor
1
C
1
V3P3SYS
V1
FDS 6531/6532 005
v1.3
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