71M6541D Maxim, 71M6541D Datasheet - Page 37
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71M6541D
Manufacturer Part Number
71M6541D
Description
The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6541D.pdf
(166 pages)
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Several UART-related registers are available for the control and buffering of serial data.
A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0
and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and
when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the
transmission by the associated UART. Received data are available by reading from the receive buffer.
Both UARTs can simultaneously transmit and receive data.
WDCON[7] (SFR 0xD8) selects whether timer 1 or the internal baud rate generator is used. All UART
transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for
variable communication baud rates from 300 to 38400 bps.
calculated.
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.
(S0RELL, S0RELH, S1RELL, S1RELH are SFR 0xAA, SFR 0xBA, SFR 0x9D and SFR 0xBB, respectively) SMOD
is the SMOD bit in the SFR PCON register (SFR 0x87). TH1(SFR 0x8D) is the high byte of timer 1.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communication in multi-processor systems. In this case, the slave processors have bit
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
the slave’s address, it sets the 9
slave processors compare the received byte with their address. If there is a match, the addressed slave
clears SM20 or SM21 and receive the rest of the message. The rest of the slave’s ignores the
message. After addressing the slave, the host outputs the rest of the message with the 9
no additional serial port receive interrupts are generated.
Rev 2
Mode 0
Mode 1
Mode 2
Mode 3
UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.
UART0
UART1
control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B)
registers for transmit and RB81 bit in S1CON[2] for receive operations.
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant
1. 8-bit serial modes with parity can be simulated by setting and reading the 9
Table 18
N/A
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of f
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud rate
generator or timer 1)
shows the selectable UART operation modes.
2
N/A
smod
* f
CKMPU
UART 0
(WDCON[7] = 0)
th
Using Timer 1
bit to 1, causing a serial port receive interrupt in all the slaves. The
Table 17: Baud Rate Generation
/ (384 * (256-TH1))
Table 18: UART Modes
CKMPU
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
N/A
N/A
2
f
CKMPU
71M6541D/F/G and 71M6542F/G Data Sheet
smod
Table 17
Using Internal Baud Rate Generator
* f
/(32 * (2
CKMPU
shows how the baud rates are
/(64 * (2
10
(WDCON[7] = 1)
-S1REL))
UART 1
10
-S0REL))
th
bit, using the
th
bit set to 0, so
37
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