71M6543F Maxim, 71M6543F Datasheet
71M6543F
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71M6543F Summary of contents
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... A Maxim Integrated Products Brand GENERAL DESCRIPTION The 71M6543F, 71M6543H, 71M6543G, and 71M6543GH are Teridian’s 4th-generation polyphase metering systems-on-chips (SoCs) with a 5MHz 8051-compatible MPU core, low-power real- time clock (RTC) with digital temperature compensation, flash memory, and LCD driver. Our Single Converter Technology® with ...
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... Data Sheet 1 Introduction ................................................................................................................................. 10 2 Hardware Description .................................................................................................................. 11 2.1 Hardware Overview............................................................................................................... 11 2.2 Analog Front-End (AFE) ........................................................................................................ 12 2.2.1 Signal Input Pins ....................................................................................................... 13 2.2.2 Input Multiplexer ........................................................................................................ 14 2.2.3 Delay Compensation ................................................................................................. 19 2.2.4 ADC Pre-Amplifier ..................................................................................................... 20 2.2.5 A/D Converter (ADC) ................................................................................................. 20 2.2.6 FIR Filter ................................................................................................................... 20 2.2.7 Voltage References ................................................................................................... 20 2.2.8 71M6xx3 Isolated Sensor Interface ............................................................................ 22 2.3 Digital Computation Engine (CE) ........................................................................................... 25 2.3.1 CE Program Memory ................................................................................................. 25 2.3.2 CE Data Memory ....................................................................................................... 25 2 ...
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... System Using Current Transformers ..................................................................................... 88 4.5 Metrology Temperature Compensation .................................................................................. 89 4.5.1 Distinction Between Standard and High-Precision Parts ............................................ 89 4.5.2 Temperature Coefficients for the 71M6543F and 71M6543G ..................................... 90 4.5.3 Temperature Coefficients for the 71M6543H and 71M6543GH .................................. 90 4.5.4 Temperature Coefficients for the 71M6xx3................................................................. 90 4.5.5 Temperature Compensation for VREF and Shunt Sensors ........................................ 90 4.5.6 Temperature Compensation of VREF and Current Transformers ............................... ...
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... Data Sheet 5.4.8 CE Transfer Variables ............................................................................................. 125 5.4.9 Pulse Generation..................................................................................................... 127 5.4.10 CE Calibration Parameters ...................................................................................... 130 5.4.11 CE Flow Diagrams .................................................................................................. 131 6 71M6543 Specifications ............................................................................................................. 133 6.1 Absolute Maximum Ratings ................................................................................................. 133 6.2 Recommended External Components ................................................................................. 134 6.3 Recommended Operating Conditions .................................................................................. 134 6.4 Performance Specifications ................................................................................................. 135 6.4.1 Input Logic Levels ................................................................................................... 135 6.4.2 Output Logic Levels ................................................................................................. 135 6 ...
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... Figure 44: Wh Error from 200 Various Frequencies (0° Load angle, 240 VAC) ............. Error! Bookmark not defined. Figure 45: 100-pin LQFP Package Outline ........................................................................................... 148 Figure 46: Pinout for the LQFP-100 Package ....................................................................................... 149 Figure 47: I/O Equivalent Circuits ......................................................................................................... 154 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 5 ...
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... Data Sheet Tables Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ......................................................... 15 Table 2. Required CE Code and Settings for CT Sensors ...................................................................... 16 Table 3: Multiplexer and ADC Configuration Bits .................................................................................... 19 Table 4. RCMD[4:0] Bits ........................................................................................................................ 23 Table 5: Remote Interface Read Commands ......................................................................................... 23 Table 6: I/O RAM Control Bits for Isolated Sensor .................................................................................. 24 Table 7: Inputs Selected in Multiplexer Cycles ...
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... Table 94: Battery Monitor Performance Specifications (TEMP_BAT = 1) ............................................... 136 Table 95: Temperature Monitor ............................................................................................................ 137 Table 96: Supply Current Performance Specifications .......................................................................... 138 Table 98: Internal Power Fault Comparators Performance Specifications ............................................. 139 Table 99: 2.5 V Voltage Regulator Performance Specifications ............................................................ 139 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 7 ...
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... Data Sheet Table 100: Low-Power Voltage Regulator Performance Specifications ................................................. 140 Table 101: Crystal Oscillator Performance Specifications ..................................................................... 140 Table 102: PLL Performance Specifications ......................................................................................... 140 Table 103: LCD Drivers Performance Specifications ............................................................................ 140 Table 105: 71M6543 VREF Performance Specifications ...................................................................... 143 Table 106: ADC Converter Performance Specifications ....................................................................... 144 Table 107: Pre-Amplifier Performance Specifications ...
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... OPT INTERFACE SEGDIO 55 OPT SEGDIO 51 / WPULSE / VBIAS VPULSE POWER FAULT WAKE DETECTION FAULTZ VSTAT v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet VREF ∆Σ_ AD CONVERTER VBIAS FIR VREF DIV MCK CK 32 ADC ...
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... Data Sheet 1 Introduction This data sheet covers the 71M6543F (64KB, 0.5%), 71M6543H (64KB, 0.1%), 71M6543G (128KB, 0.5%) and 71M6543GH (128KB, 0.1%) 4th-generation Teridian polyphase energy measurement system- on-chips (SoCs). The term “71M6543” is used when discussing a device feature or behavior that is applicable to all four part numbers. The specific part numbers are used when discussing those features that apply only to specific part numbers ...
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... The on-chip charge pump may also drive 5 V LCDs. Flexible mapping of LCD display segments facilitates the integration of existing custom LCDs. Design trade-off between the v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet and V h for four-quadrant metering. These measurements ...
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... Data Sheet number of LCD segments and DIO pins can be implemented in software to accommodate various requirements. In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on metrology and RTC accuracy (i.e., to meet the requirements of ANSI and IEC standards) ...
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... Also refer to the 71M6543 Demonstration Board schematic and bill of materials for typical component values used in these and other circuits. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet VREF IADC2 ∆Σ ADC ...
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... Data Sheet Pins IADC0-IADC1 can be programmed individually to be differential or single-ended as determined by the DIFF0_E (I/O RAM 0x210C[4]) control bit. However, for most applications, IADC0-IADC1 are configured as a differential input to work with a resistive shunt or CT directly interfaced to the IADC0- IADC1 differential input with the appropriate external signal conditioning components. ...
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... Must use the CE code that corresponds to the specific 71M6xx3 device used Teridian updates the CE code periodically. Please contact your local Teridian representative to obtain the latest CE code and the associated settings. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet I/O RAM I/O RAM Setting 1 2200[5] ...
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... Data Sheet Table 2. Required CE Code and Settings for CT Sensors I/O RAM I/O RAM Mnemonic Location FIR_LEN[1:0] 210C[2:1] 2200[5] ADC_DIV PLL_FAST 2200[4] MUX_DIV[3:0] 2100[7:4] MUX0_SEL[3:0] 2105[3:0] MUX1_SEL[3:0] 2105[7:4] MUX2_SEL[3:0] 2104[3:0] MUX3_SEL[3:0] 2104[7:4] MUX4_SEL[3:0] 2103[3:0] MUX5_SEL[3:0] 2103[7:4] MUX6_SEL[3:0] 2102[3:0] MUX7_SEL[3:0] 2102[7:4] 2101[3:0] ...
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... MUX STATE CROSS MUX_SYNC Figure 5: States in a Multiplexer Frame (MUX_DIV[3: v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 1 Figure 2, the IADC0-IADC1 input must be configured as a Figure 30 for the shunt connection details). The Figure 4. Figure 29 for the differential CT connection details). The Figure 5 ...
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... Data Sheet Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass of the CE through its code. MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by: • ...
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... This digital filter does not affect the amplitude of the signal, but provides a precisely controlled phase response. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet for the settings that are applicable to the 71M6543. 104 for more complete details about these I/O RAM locations. ...
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... Data Sheet The recommended ADC multiplexer sequence samples the current first, immediately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle Ф relative to the current. The delay compensation implemented in the CE aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i ...
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... CROSS is high, at the end of the second interval, CROSS is low. Operation with CHOP_E[1: does not require control of the chopping mechanism by the MPU. In the second toggle state, CHOP_E[1:0] = 11, CROSS does not toggle at the end of the last multiplexer cycle in an accumulation interval. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet ...
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... Data Sheet 2.2.8 71M6xx3 Isolated Sensor Interface 2.2.8.1 General Description Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M6543 via a combination of a pulse transformer and a 71M6xx3 IC (a top-level block diagram of this sensor interface 31). The 71M6xx3 receives power directly from the 71M6543 via a pulse transformer ...
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... IADC -IADC5 11 6 IADC -IADC7 Table 4. RMT_RD [15:8] TRIMT[7]=RMT_RD[8] TRIMBGB[7:0] STEMP[10:8]=RMT_RD[10:8] (RMT_RD[15: 11] are sign extended) All zeros VERSION[7:0] on page 56. on page 57. 71M6543F/H Data Sheet Control Field --- 2 TMUXR [2:0] 4 TMUXR [2:0] 6 TMUXR [2:0] RMT_RD [7:0] TRIMT[6:0]=RMT_RD[7:1] TRIMBGD[7:0] STEMP[7:0] VSENSE[7:0] All zeros TRIMT[7:0] TRIMBGB[7:0] and 4 ...
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... Data Sheet Table 6: I/O RAM Control Bits for Isolated Sensor RST Name Address Default SFR RCMD[4:0] FC[4:0] PERR_RD SFR FC[6] PERR_WR SFR FC[5] CHOPR[1:0] 2709[7:6] 00 TMUXR2[2:0] 270A[2:0] 000 TMUXR4[2:0] 270A[6:4] 000 TMUXR6[2:0] 2709[2:0] 000 2602[7:0] RMT_RD[15:8] RMT_RD[7:0] 2603[7:0] RFLY_DIS 210C[3] RMT2_E 2709[3] RMT4_E 2709[4] ...
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... For proper operation, the code pass must be completed before the multiplexer cycle ends. The CE program must begin boundary of the flash address. The I/O RAM control field CE_LCTN[6/5:0] (I/O RAM 0x2109[6/5:0]) on the 71M6543F/H and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) on the 71M6543G/GH defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[5:0] on the 71M6543F/H and 1024*CE_LCTN[6:0] on the 71M6543G/GH ...
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... Data Sheet 2.3.4 Meter Equations The 71M6543 provides hardware assistance to the CE in order to support various meter equations. This assistance is controlled through I/O RAM field EQU[2:0] (equation assist, I/O RAM 0x2106[7:5]). The Compute Engine (CE) firmware configurations can implement the equations listed in specifies the equation to be used based on the meter configuration and on the number of phases used for metering ...
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... The polarity of the pulses may be inverted with the control bit PLS_INV (I/O RAM 0x210C[0]). When PLS_INV is set, the pulses are active high. The default value for PLS_INV is zero, which selects active low pulses. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet on page 120 for details. Figure ...
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... Data Sheet The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53 (see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details). CK32 150 MUX_SYNC CE CODE ...
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... SUM_SAMPS[12:0]. Furthermore, sampling does not have to start when the line voltage crosses the zero line, and the length of the accumulation interval need not be an integer multiple of the signal cycles. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Multiplexer Frame (15 x 30.518 µs = 457.8 µs) ...
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... Data Sheet 2.4 80515 MPU Core The 71M6543 include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single machine cycle (MPU clock cycle) ...
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... By selecting the Evatronics R80515 core in the Keil compiler project settings and by using the compiler directive “MODC2”, dual data pointers are enabled in certain library routines. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 9: Memory Map Memory Name ...
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... Data Sheet An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction MOVX A,@Ri or MOVX @Ri,A. Internal Data Memory Map and Access The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory ...
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... A B 0xF0 0x00 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Description Port 0 Stack Pointer Data Pointer Low 0 Data Pointer High 0 Data Pointer Low 1 Data Pointer High 1 Power Reduction Modes, UART Speed Control Timer/Counter Control ...
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... Data Sheet Accumulator (ACC, A, SFR 0x E0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. B Register (SFR 0xF0): The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data ...
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... Idle Mode bit. To enter Idle Mode, the firmware must set the IDL bit (bit 0) in the PCON SFR register (SFR 0x87). v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 14: Port Registers (SEGDIO0-15 ...
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... Data Sheet The MPU core power consumption can be significantly reduced by the proper use of Idle Mode. The amount of power saved depends on the percentage of time spent in Idle Mode. Since some interrupts may occur frequently, thus ending Idle Mode, one method to maximize power savings using Idle Mode employ a software loop in the main background routine at a point where the MPU background processing may be permitted to idle ...
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... If set, enables serial reception. Cleared by software to disable reception. S0CON[4] REN0 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 18: UART Modes Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) Start bit, 8 data bits, stop bit, variable baud ...
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... Data Sheet Bit Symbol The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, S0CON[3] TB80 depending on the function it performs (parity check, multiprocessor communication etc.) In Modes 2 and the 9 S0CON[2] RB80 stop bit. In mode 0, this bit is not used. Must be cleared by software. ...
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... TMOD[1:0] M1:M0 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Function 13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 (SFR 0x8A or SFR 0x8B) register and the remaining 8 bits in the TH0 or TH1 (SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively). ...
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... Data Sheet Table 25: The TCON Register Bit Functions (SFR 0x88) Bit Symbol TCON[7] TF1 The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. TCON[6] TR1 Timer 1 run control bit. If cleared, Timer 1 stops. ...
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... TCON[1] IE0 External interrupt 0 flag External interrupt 0 type control bit: TCON[0] IT0 0 = interrupt on low level interrupt on falling edge. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 29 and Table Table 31). Table 36). Function Function Function Function 30) ...
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... Data Sheet Table 30: The T2CON Bit Functions (SFR 0xC8) Bit Symbol – Not used. T2CON[7] T2CON[6] I3FR Polarity control for INT3 falling edge rising edge. Polarity control for INT2: T2CON[5] I2FR 0 = falling edge rising edge. T2CON[4:0] – Not used. ...
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... Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in Table 35) by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 33: Interrupt Enable and Flag Interrupt Flag Name Location ...
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... Data Sheet IP1(SFR 0xB9) (Table 36). If requests of the same priority level are received simultaneously, an internal polling sequence as shown in Table 37 Changing interrupt priorities while interrupts are enabled can easily cause software defects best to set the interrupt priority registers only once during initialization before interrupts are enabled. ...
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... TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 37: Interrupt Polling Sequence External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt ...
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... Data Sheet ...
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... Physical Memory 2.5.1.1 Flash Memory The device includes 64 KB (71M6543F/H) or 128 KB (71M6543G/GH) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations ...
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... Data Sheet The page erase sequence is: • Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]). • Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94). Bank-Switching in the 71M6543G/GH The 128 KB program memory in the 71M6543G/GH consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF ...
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... R/W Inhibits erasure of page 0 and flash addresses above the beginning of CE code as defined by CE_LCTN[6/5:0](I/O RAM 0x2109[5:0]) on the 71M6543F/H and CE_LCTN[6:0] I/O RAM 0x2109[6:0]) on the 71M6543G/GH. Also inhibits the read of flash via the ICE and SPI ports. 2.5.12 SPI Slave Port. Table 69 ...
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... Data Sheet Although the oscillator may appear to work when VBAT is not connected, this mode of operation is not re- commended. If VBAT_RTC is connected to a drained battery or disconnected, a battery test that sets TEMP_BAT may drain the supply connected to VBAT_RTC and cause the oscillator to stop. A stopped oscillator may force the device to reset ...
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... The RTC is capable of processing leap years. Each counter has its own output register. The RTC chain registers are not be affected by the reset pin, watchdog timer resets transitions between the battery modes and mission mode. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 42: Clock System Summary Fixed Frequency or Range PLL_FAST=1 PLL_FAST=0 32 ...
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... Data Sheet Name Location Rst 2504[6:0] 40 RTCA_ADJ[6:0] RTC_P[16:14] 289B[2:0] 289C[7:0] RTC_P[13:6] 289D[7:2] RTC_P[5:0] RTC_Q[1:0] 289D[1:0] RTC_RD 2890[6] RTC_WR 2890[7] RTC_FAIL 2890[4] RTC_SBSC[7:0] 2892[7:0] 2.5.4.3 RTC Rate Control The 71M6543 has two rate adjustment mechanisms: • The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register RTCA_ADJ[6:0], that trims the crystal load capacitance. • ...
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... Referring to Figure 13 the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] right-shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP[10:0]/4). A v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 32768 ⋅ RTC_P ...
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... Data Sheet limiter ensures that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). The 8-bit NV RAM content pointed to by the address is added as a 2’s complement value to 0x40000, the nominal value of 4*RTC_P[16:0] + RTC_Q[1:0]. Refer to 2 ...
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... MSN mode and TEMP_PWR = 1. The second equation applies when the 71M6543F and 71M6543G are in BRN mode, and in this case, the TEMP_PWR and TEMP_BSEL bits must both be set to the same value, so that the battery that supplies the temperature sensor is also the battery that is measured and reported in BSENSE ...
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... Data Sheet Table 46 shows the I/O RAM registers used for temperature and battery measurement. If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature measurement may not finish. In this case, firmware may complete the measurement by selecting V3P3D (TEMP_PWR = 1). ...
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... When not needed for UART1, OPT_TX can alternatively be configured as SEGDIO51. Configuration is via the OPT_TXE[1:0] (I/O RAM 0x2456[3:2]) field and LCD_MAP[51] (I/O RAM 0x2405[0]). The v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 4.5 Metrology Temperature Compensation on page 22 for information on how to read the ...
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... Data Sheet OPT_TXE[1:0] field allows the MPU to select VPULSE, WPULSE, SEGDIO51 or the output of the pulse modulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be configured as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]). ...
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... Violating this rule leads to increased quiescent current in sleep and LCD modes. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 48) is configured as a DIO output pin with a value of 1 (high) by Resource Selected for SEGDIOn or PB Pin ...
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... Data Sheet MISSION LCD/SLEEP BROWNOUT HIGH HIGH-Z LOW Not recommended Figure 16: Connecting an External Load to DIO Pins 2.5.10.2 Combined DIO and SEG Pins A total of 51 combined DIO/LCD pins are available. These pins can be categorized as follows: 39 combined DIO/LCD segment pins: SEGDIO4…SEGDIO25 (22 pins) o SEGDIO28… ...
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... SEG Data Register 32 DIO Data Register 32 Direction Register input output Table 51: Data/Direction Registers for SEGDIO51 to SEGDIO55 SEGDIO Pin # Configuration DIO LCD SEG Data Register v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet ...
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... Data Sheet DIO Data Register Direction Register input output 2.5.10.3 LCD Drivers The LCD drivers are grouped into up to six commons (COM0 – COM5) and segment drivers. The LCD interface is flexible and can drive 7-segment digits, 14-segment digits or enunciator symbols. ...
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... LCD display or turn it fully on. Neither bit affects the contents of the LCD data stored in the LCDSEG_DIO[ ] registers. In comparison, LCD_RST (I/O RAM 0x240C[2]) clears all LCD data to zero. LCD_RST affects only pins that are configured as LCD. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 52: LCD_VMODE Configurations 0 0 External VLCD connected to the VLCD pin. ...
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... Data Sheet A small amount of power can be saved by programming the LCD frequency to the lowest value that provides satisfactory LCD visibility over the required temperature range. Table 53 shows all I/O RAM registers that control the operation of the LCD interface. Name Location Rst ...
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... SEG pins or their alternate function (see pins 93 and 92 in then the pins are configured as SEG pins. If the LCD_MAP[47:46] bits are 0, then the pins are configured as their alternate functions (TMUX2OUT and TMUXOUT, respectively). v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 1/2 BIAS, 2 STATES (LCD_MODE = 010 ) 0 1 COM0 ...
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... Data Sheet For example, if LCD_MAP[46 then pin 93 (TMUX2OUT/SEG46) is configured as SEG46, and if LCD_MAP[46]=0, then pin 93 is configured as TMUX2OUT. The SEG pins with alternate ICE interface function (see pins 56-58 in alternate ICE interface function (i.e., E_RXTX, E_TCLK and E_RST) if the ICE_E pin (pin 59) is driven high, and in this case, the bits LCD_MAP[50:48] (I/O RAM 0x2405[2:0]) bits are “ ...
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... Figure 18: 3-wire Interface. Write Command, HiZ=0. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Description Wait for Ready. If this bit is set, the trailing edge of BUSY is delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence ...
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... Data Sheet EECTRL Byte Written Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) Figure 19: 3-wire Interface. Write Command, HiZ=1 EECTRL Byte Written READ SCLK (output) SDATA (input) SDATA output Z BUSY (bit) Figure 20: 3-wire Interface. Read Command. ...
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... Transaction not ending on a byte boundary. SPI Safe Mode v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 57: SPI Transaction Fields Size Description (bytes) 16-bit address. The address field is not required if the transaction simple SPI command ...
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... Data Sheet Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte transfer region at address 0x400 to 0x40F ...
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... The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Wk Dir Description ...
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... Data Sheet disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This sequential write process prevents inadvertent entering of SFM. The sequence for invoking SFM is: • First, write to SFMM (I/O RAM 0x2080) register. The value written to this register defines the SFM mode. ...
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... TMUX[5:0] All values which are not shown are reserved. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 60: TMUX[4:0] Selections Description 32.768 kHz clock waveform Indicates when the MPU has reset the watchdog timer. Can be monitored to determine spare time in the watchdog timer. ...
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... Data Sheet Signal Name TMUX2[4:0] 0 WD_OVF 1 PULSE_1S 2 PULSE_4S 3 RTCLK SPARE[1] bit – I/O RAM 8 0x2704[1] SPARE[2] bit – I/O RAM 9 0x2704[2] A WAKE B MUX_SYNC C MCK E GNDD 12 INT0 – DIG I/O 13 INT1 – DIG I/O 14 INT2 – CE_PULSE 15 INT3 – CE_BUSY 16 INT4 - VSTAT 17 INT5 – EEPROM/SPI 18 INT6 – ...
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... Shortly after system power (V3P3SYS) is applied, the 71M6543 is in mission mode (MSN mode). MSN mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operating mode where the part is capable of measuring energy. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet t ∫ ...
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... Data Sheet When system power is not available, the 71M6543 is in one of three battery modes: • BRN mode (brownout mode) • LCD mode (LCD-only mode) • SLP mode (sleep mode). An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are typically connected together at the PCB level) ...
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... PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in LCD mode, otherwise the PLL is de-activated. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 62: Available Circuit Functions System Power BRN (Brownout Mode) ...
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... Data Sheet 3.2.1 BRN Mode In BRN mode, most non-metering digital functions are active (as shown in EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN mode the MPU to scale down the PLL (using PLL_FAST, I/O RAM 0x2200[4]) or the MPU frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order to save power ...
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... After the transition from SLP mode to MSN or BRN mode the 0x0000, the XRAM undefined state, and the I/O RAM is only partially preserved (see the description of I/O RAM states in 5.2). The non-volatile sections of the I/O RAM are preserved unless RESET goes high. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 3.4 Wake-Up 3.4 Wake-Up Behavior. Behavior. ...
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... Data Sheet 3.3 Fault and Reset Behavior 3.3.1 Events at Power-Down Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage ...
Page 81
... WD overflow event or after a power-up. The WF_OVF bit is cleared by the RESET pin. There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT can be disabled by raising the ICE_E pin to 3.3 VDC. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 81 ...
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... Data Sheet In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit I/O RAM 0x28B4[7]). The watchdog timer is also reset when the 71M6543 wakes from LCD or SLP mode, and when ICE_E=1. 3.4 Wake-Up Behavior As described above, the part always wakes up in MSN mode when system power is restored. As stated in 3 ...
Page 83
... WF_RST 28B0[6] * WF_RSTBIT 28B0[5] * WF_ERST 28B0[3] * WF_CSTART 28B0[7] * WF_BADVDD 28B0[2] * v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Wake Flag De-bounce Location 28B0[4] No 28B0[7] No 28B0[2] No Table 65: Wake Bits WK Dir Description Connects SEGDIO4 to the WAKE logic and permits – R/W SEGDIO4 rising to wake the part ...
Page 84
... Data Sheet Flag Timer expiration WF_TMR WF_PB PB pin high level WF_RX Either edge RX pin SEGDIO4 rising edge WF_DIO4 WF_DIO52 SEGDIO52 high level If OPT_RXDIS = 1 (I/O RAM 0x2457[2]), wake on SEGDIO55 high WF_DIO55 If OPT_RXDIS = 0 wake on either edge of OPT_RX RESET pin driven high ...
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... CESTATUS register at every occurrence of the CE_BUSY interrupt in order to detect sag or zero crossing events. Refer to 5.4 CE Interface Description using the MPU firmware. Samples MUX v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet and V h for four-quadrant metering. These measurements on page 120 for additional information on setting up the device Pulses ...
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... Data Sheet 4 Application Information 4.1 Connecting 5 V Devices All digital input pins of the 71M6543 are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. 4.2 Directly Connected Sensors Figure 27 through ...
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... NEUTRAL B A Pulse Transformers AMR IR HOST Figure 31: System Using Three-Remotes and One-Local (Neutral) Sensor v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 2.2.8 71M6xx3 Isolated Sensor Interface Figure 31. LOAD POWER SUPPLY NEUTRAL Note: This system is referenced to Neutral 3x TERIDIAN 71M6xx3 ...
Page 88
... Data Sheet 4.4 System Using Current Transformers Figure 32 shows a polyphase system using four current transformers to support optional Neutral current sensing for anti-tamper purposes. The Neutral current sensing CT can be omitted if Neutral current sensing is not required. The system is referenced to Neutral (i.e., the Neutral rail is tied to V3P3A and V3P3SYS) ...
Page 89
... The principal remaining error sources are the current sensors (shunts or CTs) and their corresponding signal conditioning circuits, and the resistor voltage divider used to measure the voltage. The 71M6543F and 71M6543G 0.5% grade devices should be used in Class 1% designs, to allow margin for the other error sources in the system. ...
Page 90
... Refer to the 71M6xxx Data Sheet for details. 4.5.2 Temperature Coefficients for the 71M6543F and 71M6543G The equations provided below for calculating TC1 and TC2 apply to the 71M6543F and 71M6543G (0.5% energy accuracy). In order to obtain TC1 and TC2, the MPU reads TRIMT[7:0] (I/O RAM 0x2309) and uses the TC1 and TC2 equations provided. PPMC and PPMC2 are then calculated from TC1 and TC2, as shown. The resulting tracking of the reference voltage (VREF) is within ± ...
Page 91
... Local / 3 Remote configuration shown in Table 67: GAIN_ADJn Compensation Channels Gain Adjustment Output CE RAM Address GAIN_ADJ0 GAIN_ADJ1 GAIN_ADJ2 GAIN_ADJ3 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 27) determine the behavior of the voltage division ratio with respect to ⋅ ⋅ 10 TEMP _ X PPMC 100 ...
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... In the 71M6543F and 71M6543G, the required VREF compensation coefficients PPMC and PPMC2 are calculated from readable on-chip non-volatile fuses (see 71M6543F). These coefficients are designed to achieve ±40 ppm/°C for VREF in the 71M6543F and 71M6543G. PPMC and PPMC2 coefficients are similarly calculated for the 71M6xx3 remote sensor (see 4 ...
Page 93
... CT and burden resistor for current channels or the resistor divider network for the voltage channels). In the 71M6543F and 71M6543G (±0.5% energy accuracy), the required VREF compensation coefficients PPMC and PPMC2 are calculated from readable on-chip non-volatile fuses (see Coefficients for the 71M6543F). These coefficients are designed to achieve ± ...
Page 94
... Data Sheet behavior of each individual part across industrial temperatures (see the 71M6543H). The resulting tracking of the reference VREF voltage is within ±10 ppm/°C. 2 4.6 Connecting I C EEPROMs EEPROMs or other I C compatible devices should be connected to the DIO pins SEGDIO2 and ...
Page 95
... R1 should be in the range of 100Ω and mounted as closely as possible to the IC. Since the 71M6543 generates its own power-on reset, a reset button or circuitry, as shown in only required for test units and prototypes. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet V3P3SYS R 1 100 pF 10 kΩ ...
Page 96
... Data Sheet VBAT/ V3P3D Ω Reset Switch 0.1µF Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) 4.11 Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection ...
Page 97
... Vrms, Irms), and auto-calibration. Teridian provides a calibration spreadsheet file to facilitate the calibration process. Contact your Teridian representative to obtain a copy of the latest calibration spreadsheet file for the 71M6543. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 97 ...
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... Data Sheet 5 Firmware Interface 5.1 I/O RAM Map –Functional Order In Table 69 and Table 70, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’. Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with an ‘ ...
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... U U DIO_R11[2:0] DIO_R9[2:0] DIO_R7[2:0] DIO_R5[2:0] DIO_R3[2: OPT_FDC[1: EX_YPULSE EX_RTCT EX_VPULSE EW_RX SFMM[7:0]* SFMS[7:0]* 2.5.1.1 Flash Memory © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Bit 3 Bit 2 Bit 1 LCD_BLNKMAP22[5:0] U DIO_RPB[2:0] U DIO_R10[2:0] U DIO_R8[2:0] U DIO_R6[2:0] U DIO_R4[2:0] U DIO_R2[2:0] OPT_TXE[1:0] OPT_TXMOD U OPT_RXDIS ...
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... Data Sheet Table 70 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background. Name Addr Bit 7 Bit 6 CE and ADC MUX5 2100 MUX4 ...
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... DIO_R7[2:0] DIO_R5[2:0] DIO_R3[2: OPT_FDC[1: RTCA_ADJ[6:0] © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Bit 3 Bit 2 Bit 1 U LCD_RST LCD_BLANK LCD_DAC[4:0] LCD_SEG0[5:0] … LCD_SEG15[5:0] LCD_SEGDIO16[5:0] … LCD_SEGDIO45[5:0] LCD_SEG46[5:0] … LCD_SEG50[5:0] LCD_SEGDIO51[5:0] … LCD_SEGDIO55[5:0] ...
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... Data Sheet Name Addr Bit 7 Bit 6 REMOTE2 2602 REMOTE1 2603 RBITS INT1_E 2700 EX_EEX EX_XPULSE INT2_E 2701 EX_SPI EX_WPULSE SECURE 2702 FLSH_UNLOCK[3:0] Analog0 2704 VREF_CAL VREF_DIS VERSION 2706 INTBITS 2707 U INT6 FLAG0 SFR E8 IE_EEX IE_XPULSE FLAG1 SFR F8 IE_SPI ...
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... U U EW_RX U U DIO_DIR[15:12] DIO_DIR[11:8] DIO_DIR[7:4] DIO_DIR[3:0] FLSH_ERASE[7: FLSH_PEND FLSH_PGADR[5:0] EEDATA[7:0] EECTRL[7:0] © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Bit 3 Bit 2 Bit 1 RTC_HR[4:0] U RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] U RTC_P[16:14] RTC_Q[1:0] RTC_TMIN[5:0] RTC_THR[4:0] TEMP_PER[2:0] WF_BADVDD U WF_PB WF_DIO4 WF_DIO52 ...
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... Data Sheet 5.2 I/O RAM Map – Alphabetical Order Table 71 lists I/O RAM bits and registers in alphabetical order. Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the address space 0x2XXX ...
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... The value on the first 16 DIO pins. Pins configured as LCD read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input ignore F R/W writes. Note that the data for DIO pins above 15 is set by SEGDIOx[0]. © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 11 = toggle MULTIPLE – ...
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... Data Sheet Name Location Rst Wk Dir DIO_EEX[1:0] 2456[7:6] 0 2457[6] 0 DIO_PV DIO_PW 2457[7] 0 DIO_PX 2458[7] 0 DIO_PY 2458[6] 0 EEDATA[7:0] SFR 9E 0 EECTRL[7:0] SFR 9F 0 2106[7:5] 0 EQU[2:0] 106 Description When set, converts SEGDIO3 and SEGDIO2 to interface with external EEPROM. SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional SDATA, but only if LCD_MAP[2] and LCD_MAP[3] are cleared ...
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... PLL_FAST = 0: FIR_LEN[1:0] The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting. Refer to Table 83 on page 126 and Table 105 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet , for details. for de-bounce issues. ADC Cycles 00 141 01 288 10 ...
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... Data Sheet Name Location Rst Wk Dir FL_BANK[1:0] SFR B6[1: R/W FLSH_ERASE[7:0] SFR 94[7:0] 0 FLSH_MEEN SFR B2[1] 0 SFR B2[3] 0 FLSH_PEND FLSH_PGADR[5:0] SFR B7[7:2] 0 FLSH_PSTWR SFR B2[2] 0 108 Description Flash Bank Selection (71M6543G and 71M6543GH only) The program memory of the 71M6543G/GH consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF ...
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... R/W blink. The most significant bit corresponds to COM5, the least significant, to COM0. Sets the LCD clock frequency. Note: f LCD_CLK[1:0] 00 – R © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet = 32768 Hz XTAL LCD Clock Frequency XTAL XTAL ...
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... Data Sheet Name Location Rst Wk Dir LCD_DAC[4:0] 240D[4:0] 0 2400[7] 0 LCD_E LCD_MAP[55:48] 2405[7:0] 0 LCD_MAP[47:40] 2406[7:0] 0 2407[7:0] 0 LCD_MAP[39:32] LCD_MAP[31:24] 2408[7:0] 0 LCD_MAP[23:16] 2409[7:0] 0 LCD_MAP[15:8] 240A[7:0] 0 LCD_MAP[7:0] 240B[7:0] 0 LCD_MODE[2:0] 2400[6:4] 0 LCD_ON 240C[0] 0 LCD_BLANK 240C[1] 0 LCD_ONLY 28B2[6] 0 240C[2] 0 LCD_RST LCD_SEG0[5:0] 2410[5: 241F[5:0] ...
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... Selects which ADC input converted during time slot 5. 0 R/W Selects which ADC input converted during time slot 6. 0 R/W Selects which ADC input converted during time slot 7. © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 2.5.10.3 for the definition of V3P3L. -(2+ MPU_DIV [2:0]) . 111 ...
Page 112
... Data Sheet Name Location Rst Wk Dir 2101[3:0] 0 MUX8_SEL[3:0] MUX9_SEL[3:0] 2101[7:4] 0 MUX10_SEL[3:0] 2100[3:0] 0 MUX_DIV[3:0] 2100[7:4] 0 OPT_BB 2457[0] 0 OPT_FDC[1:0] 2457[5:4] 0 OPT_RXDIS 2457[2] 0 OPT_RXINV 2457[1] 0 OPT_TXE [1,0] 2456[3:2] 00 – OPT_TXINV 2456[0] 0 OPT_TXMOD 2456[1] 0 OSC_COMP 28A0[5] 0 PB_STATE SFR F8[0] 0 PERR_RD SFR FC[6] 0 PERR_WR SFR FC[5] 112 ...
Page 113
... Controls how the 71M6543 drives the power pulse for the 71M6xxx. When set, the 0 R/W power pulse is driven high and low. When cleared driven high followed by an open circuit fly-back interval. © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet is PLS_INTERVAL[7:0] in units of CK_FIR I 2.3.6.2 113 ...
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... Data Sheet Name Location Rst Wk Dir 2709[3] RMT2_E RMT4_E 2709[4] 0 RMT6_E 2709[5] RMT_RD[15:8] 2602[7:0] 0 2603[7:0] RMT_RD[7:0] RTCA_ADJ[6:0] 2504[6:0] 40 – RTC_FAIL 2890[4] 0 RTC_P[16:14] 289B[2:0] 4 RTC_P[13:6] 289C[7:0] 0 RTC_P[5:0] 289D[7:2] 0 289D[1:0] 0 RTC_Q[1:0] RTC_RD 2890[6] 0 RTC_SBSC[7:0] 2892[7:0] – RTC_TMIN[5:0] 289E[5:0] 0 RTC_THR[4:0] 289F[4:0] ...
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... Indicates that hardware is still writing the 0x28A0 byte. Additional writes to this byte are 0 R locked out while it is one. Write duration could be as long as 6 ms. – R Storage location for STEMP[10:0] at 22C. STEMP[10: bit word. © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 115 ...
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... Data Sheet Name Location Rst Wk Dir 28A0[4] 0 TEMP_BAT TEMP_BSEL 28A0[7] 0 28A0[2:0] 0 TEMP_PER[2:0] 28A0[6] 0 TEMP_PWR TEMP_START 28B4[6] 0 TMUX[5:0] 2502[5:0] – 2503[4:0] – TMUX2[4:0] TMUXR2[2:0] 270A[2:0] TMUXR4[2:0] 270A[6:4] 000 000 R/W TMUXR6[2:0] 2709[2:0] VERSION[7:0] 2706[7:0] – VREF_CAL 2704[7] 0 VREF_DIS 2704[6] 0 116 Description – ...
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... Indicates that RX caused the part to wake. Indicates that the Reset pin, Reset bit, ERST pin, Watchdog timer, the cold start detector, – bad VBAT caused the part to reset. © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 117 ...
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... Data Sheet 5.3 Reading the Info Page (71M6543H and 71M6543GH only) High precision trim fuse values provided in the 71M6543H and 71M6543GH devices cannot be directly accessed through the I/O RAM space. These trim fuses reside in a special area termed the “Info Page”. ...
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... INFO_PG = *px; INFO_PG = 0; break; case _TRIMBGB: INFO_PG = *(uint16r_t*)px; INFO_PG = 0; break; case _TEMP85: INFO_PG = *(uint16r_t*)px; INFO_PG = & 0x800 0xF800; break; } return (x); } #endif //#if HIGH_PRECISION_METER v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 119 ...
Page 120
... Data Sheet 5.4 CE Interface Description 5.4.1 CE Program The CE performs the precision computations necessary to accurately measure power. These computations include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase measurement. All data computed by the CE is dependent on the selected meter equation as given by EQU[2:0] (I/O RAM 0x2106[7:5]) ...
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... Before starting the CE using the CE_E bit (I/O RAM 0x2106[0]), the MPU has to establish the proper environment for the CE by implementing the following steps: • Locate the CE code in Flash memory using CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) in the 71M6543F/H and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) in the 71M6543G/GH • ...
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... Data Sheet 5.4.6 CE Front-End Data (Raw Data) Access to the raw data provided by the AFE is possible by reading CE RAM addresses 0 through A, as shown in Table 74. In the expression MUXn_SEL[3: ‘n’ refers to the multiplexer frame time slot number and ‘x’ refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10, or simply decimal) ...
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... WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88). The 71M6543 Demo Code creep function halts both internal and external pulse generation. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 75: CESTATUS Register Description See description of CESTATUS bits in Table 76: CESTATUS Bit Definitions (Table 77) ...
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... Data Sheet Table 78: CECONFIG Bit Definitions (CE RAM 0x20) CECONFIG Name Default bit 23 Reserved 22 EXT_TEMP 21 EDGE_INT 20 SAG_INT 19:8 SAG_CNT (0xDA) 7:6 FREQSEL[1:0] 5 EXT_PULSE 4:2 Reserved 1 PULSE_FAST 0 PULSE_SLOW The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag interrupt. Thus, a SAG_INT event occurs when the selected phase has satisfied the sag event criteria as set by the SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]) ...
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... VAR1SUM_X 0x8B VAR2SUM_X v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Description The voltage threshold for sag warnings. The default value is 7 equivalent RMS if VMAX = 600 V. The assignments of these gain adjustments depends on the meter design. See 4 ...
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... Data Sheet Table 81: CE Transfer Variables (with CTs) CE Name Address 0x84 WSUM_X The signed sum: W0SUM_X+W1SUM_X+W2SUM_X. 0x85 W0SUM_X The sum of Wh samples from each wattmeter 0x86 element. W1SUM_X 0x87 W2SUM_X 0x88 VARSUM_X The signed sum: VAR0SUM_X+VAR1SUM_X+VAR2SUM_X. 0x89 VAR0SUM_X The sum of VARh samples from each wattmeter element ...
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... Control is transferred to the MPU for pulse generation if EXT_PULSE = 1 (CE RAM 0x20[5]). In this case, the pulse rate is determined by APULSEW and APULSER (CE RAM 0x45 and 0x49). The MPU has to load v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet ⋅ VxSQSUM F ...
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... Data Sheet the source for pulse generation in APULSEW and APULSER to generate pulses. Irrespective of the EXT_PULSE status, the output pulse rate controlled by APULSEW and APULSER is implemented by the CE only. By setting EXT_PULSE = 1, the MPU is providing the source for pulse generation. If EXT_PULSE is 0, W0SUM_X and VAR0SUM_X are the default pulse generation sources ...
Page 129
... LSB QUANT _ VARx _ LSB v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet 0 Compensation factors for truncation and noise in current, real 0 energy and reactive energy for phase Compensation factors for truncation and noise in current, real 0 energy and reactive energy for phase B. ...
Page 130
... Data Sheet 5.4.10 CE Calibration Parameters Table 87 lists the parameters that are typically entered to effect calibration of meter accuracy. CE Defau Name Address lt 0x10 CAL_IA 16384 0x11 CAL_VA 16384 0x13 CAL_IB 16384 0x14 16384 CAL_VB 0x16 CAL_IC 16384 0x17 CAL_VC 16384 0x19 ...
Page 131
... 2184 Hz S Figure 39: CE Data Flow: Multiplexer and ADC Figure 40: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet VREF de - multiplexer ∑ ∆ Deci - mator mod F ...
Page 132
... Data Sheet VARA VARB VARC SQUARE Figure 41: CE Data Flow: Squaring and Summation Stages 132 © 2008–2011 Teridian Semiconductor Corporation SUM Σ Σ SUM_SAMPS = 2184 IASQ SUM IBSQ Σ ICSQ VASQ I 2 VBSQ ...
Page 133
... Outputs (TX) Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Soldering temperature – 10 second duration v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 88: Absolute Maximum Ratings Voltage and Current Temperature −0 +4 +4 +0 +10 mA, -0 ...
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... Data Sheet 6.2 Recommended External Components Table 89: Recommended External Components Name From To C1 V3P3A GNDA C2 V3P3D GNDD CSYS V3P3SYS GNDD CVDD VDD GNDD CVLCD VLCD GNDD XTAL XIN XOUT CXS XIN GNDA CXL XOUT GNDA 6.3 Recommended Operating Conditions Unless otherwise specified, all parameters listed under ...
Page 135
... Note: 1. Guaranteed by design; not production tested. 2. Caution: The sum of all pull up currents must be compatible with the on-resistance of the internal V3P3D switch. See v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 91: Input Logic Levels Condition , VIN=0 V, ICE_E=3.3 V ...
Page 136
... Data Sheet 6.4.3 Battery Monitor Table 93: Battery Monitor Performance Specifications (TEMP_BAT = 1) Parameter BV: Battery Voltage (definition) Measurement Error BV ⋅ − 100 1 VBAT Input impedance in continuous measurement, MSN mode. V(VBAT_RTC)/I(VBAT_RTC) Load applied with BCURR ...
Page 137
... TEMP_START (see note 1) Notes: 1. Guaranteed by design; not production tested. 2. For the 71M6543F and 71M6543G, TEMP_85 fuses read 0. 3. For the 71M6543H and 71M6543GH, TEMP_85 fuses ≠ The coefficients provided in these equations are typical. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet ...
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... Data Sheet 6.4.5 Supply Current The supply currents provided in Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x03 remote sensor. Table 95: Supply Current Performance Specifications Parameter Condition Polyphase: 4 Currents, 3 Voltages V3P3A = V3P3SYS = 3.3 V, I1: MPU_DIV [2:0]= 3 (614 kHz MPU clock), ...
Page 139
... V Comparator 2.0 V Comparator 6.4.8 2.5 V Voltage Regulator – System Power Table 98: 2.5 V Voltage Regulator Performance Specifications Parameter V2P5 V2P5 load regulation Voltage overhead V3P3SYS-V2P5 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Condition Min | ≤ V3P3D | ≤ V3P3D VBAT>2.5V ...
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... Data Sheet 6.4.9 2.5 V Voltage Regulator – Battery Power Table 99: Low-Power Voltage Regulator Performance Specifications Parameter V2P5 V2P5 load regulation Voltage Overhead 2V − VBAT-VDD 6.4.10 Crystal Oscillator Table 100: Crystal Oscillator Performance Specifications Parameter Maximum Output Power to Crystal XIN to XOUT Capacitance ...
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... LCD_DAC Error. VLCD-VLCDnom DAC=12, no Boost V3P3 = 3.6 V V3P3 = 3.0 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode VBAT = 2.5 V, V3P3 = 0 V, BRN Mode v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Condition V3P3 = 3.3 V, RVLCD=removed, LCD_BAT=0, LCD_VMODE[1:0]=0, ∆ILCD=10 µA V3P3 = 0 V, VBAT = 2.5 V, RVLCD =removed, LCD_BAT =1, LCD_VMODE[1:0]=0, ∆ ...
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... Data Sheet Parameter LCD_DAC Error. VLCD-VLCDnom Zero Scale, no Boost V3P3 = 3.6 V V3P3 = 3.0 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom Full Scale, with Boost, LCD mode VBAT = 4.0 V, V3P3 = 0 V VBAT = 2.5 V, V3P3 = 0 V Note: 1. Guaranteed by design; not production tested. ...
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... VNOM temperature coefficients: TC1 = TC2 = VREF(T) deviation from VNOM(T) (see note 1): − 6 VREF ( T ) VNOM ( VNOM ( temperature characterization trim information is not available (71M6543F and 71M6543G , 0.5%) VNOM temperature coefficients: TC1 = TC2 = VREF(T) deviation from VNOM(T) (see note 1): − 6 VREF ( T ) VNOM ( VNOM ( T ) ...
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... Data Sheet 6.4.15 ADC Converter Table 105: ADC Converter Performance Specifications Parameter Recommended Input Range (Vin - V3P3A) Voltage to Current Crosstalk Vcrosstalk ∠ − ∠ cos( Vin Vcrosstalk Vin (see note 1) Input Impedance, no pre-amp DC Gain Error vs %Power Supply A Variation ∆ ...
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... Vin=30mV differential Vin=15mV differential Preamp Offset IADC0=IADC1=V3P3+30mV IADC0=IADC1= V3P3+15mV IADC0=IADC1= V3P3 IADC0=IADC1= V3P3-15mV IADC0=IADC1= V3P3-30mV Note: 1. Guaranteed by design; not production tested. v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Condition Min CONDITION MIN T = 5⁰C, A V3P3=3.3 V, PRE_E=1, 7.8 FIR_LEN=2, 7 ...
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... Data Sheet 6.5 Timing Specifications 6.5.1 Flash Memory Table 107: Flash Memory Timing Specifications Parameter Flash write cycles Flash data retention Flash byte writes between page or mass erase operations Write Time per Byte Page Erase (1024 bytes) Mass Erase 6.5.2 SPI Slave Table 108 ...
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... Reset pulse fall time (see note 1) Note: 1. Guaranteed by design; not production tested. 6.5.5 Real-Time Clock (RTC) Parameter Range for date v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 110: RESET Pin Timing Condition Table 111: RTC Range for Date Condition Min Typ Max ...
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... Data Sheet 6.6 100-Pin LQFP Package Outline Drawing Controlling dimensions are in mm. 1 14.000 +/- 0.200 0.225 +/- 0.045 Figure 42: 100-pin LQFP Package Outline 148 © 2008–2011 Teridian Semiconductor Corporation 15.7(0.618) 16.3(0.641) Top View MAX. 1.600 1.50 +/- 0.10 0.50 TYP. 0.10 +/- 0.10 Side View 0.60 TYP> v1.2 ...
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... SEGDIO27/COM4 16 SEGDIO26/COM5 17 SEGDIO25 18 SEGDIO24 19 SEGDIO23 20 SEGDIO22 21 SEGDIO21 22 SEGDIO20 23 SEGDIO19 24 SEGDIO18 25 Figure 43: Pinout for the LQFP-100 Package v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Teridian 71M6543F 71M6543H 71M6543G 71M6543GH XIN GNDA 72 VBAT_RTC 71 VBAT 70 V3P3SYS 69 IADC2 68 67 ...
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... Data Sheet 6.8 71M6543 Pin Descriptions 6.8.1 71M6543 Power and Ground Pins Pin types Power Output Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under Section Table 112: 71M6543 Power and Ground Pins Pin Name Type 72, 80 GNDA ...
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... I 76 XOUT O v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Table 113: 71M6543 Analog Pins Circuit Differential or Single-Ended Analog Line Current Sense Inputs. These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of current sensors. Unused pins must be connected to V3P3A ...
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... Data Sheet 6.8.3 71M6543 Digital Pins Pin types Power Output Input, I/O = Input/Output, N connect. The circuit number denotes the equivalent circuit, as specified in Section 6.8.4. Pin Name 12–15 COM0–COM3 SEGDIO0/WPULSE 45 44 SEGDIO1/VPULSE 43 SEGDIO2/SDCK 42 SEGDIO3/SDATA 41 SEGDIO4 39 SEGDIO5 38 SEGDIO6/XPULSE 37 SEGDIO7/YPULSE 36 SEGDIO8/DI 35–27 SEGDIO[9:17] 25– ...
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... NC 74, 77, 78, 79 v1.2 © 2008–2011 Teridian Semiconductor Corporation 71M6543F/H and 71M6543G/GH Data Sheet Type Circuit Chip Reset. This input pin is used to reset the chip into a known state. For normal operation, this pin is pulled low reset the chip, this pin should be pulled high. This pin has an internal 30 μ ...
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... Data Sheet 6.8.4 I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin 110K GNDD GNDD Digital Input ...
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... Future product—contact factory for availability. 8 Related Information The following documents related to the 71M6543 and 71M6xx3 are available from Teridian Semiconductor Corporation: • 71M6543F/H and 71M6543G/GH Data Sheet (this document) • 71M6xxx Data Sheet • 71M654x Software User’s Guide (SUG) • ...
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... Data Sheet Appendix A: Acronyms AFE Analog Front-End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response Inter-IC Bus ICE In-Circuit Emulator IEC International Electrotechnical Commission ...
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... 2011 Maxim Integrated Products 71M6543F/H and 71M6543G/GH Data Sheet DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products ...