71M6543F Maxim, 71M6543F Datasheet - Page 60

• Manufacturer Part Number: 71M6543F
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

12 combined DIO/LCD segment pins shared with other functions:
Additionally, 5 LCD segment (SEG) pins are available. These pins can be categorized as follows:
Thus, a total of 51 DIO pins are available with minimum LCD configuration, and a total of 56 LCD pins are
available with minimum DIO configuration.
71M6543F/H and 71M6543G/GH Data Sheet
2.5.10.2 Combined DIO and SEG Pins
A total of 51 combined DIO/LCD pins are available. These pins can be categorized as follows:
39 combined DIO/LCD segment pins:
60
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
SEGDIO
Table 48: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15
o
o
o
o
o
o
o
o
o
o
o
Pin #
SEGDIO4…SEGDIO25 (22 pins)
SEGDIO28…SEGDIO35 (8 pins)
SEGDIO40…SEGDIO45 (6 pins)
SEGDIO52…SEGDIO54 (3 pins)
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
3 SEG pins combined with the ICE interface (SEG48/E_RXTX, SEG49/E_TCLK,
SEG50/E_RST)
2 SEG pins combined with the test multiplexer outputs (SEG46/TMUX2OUT,
SEG47/TMUXOUT)
Not recommended
45
0
0
0
0
4
HIGH-Z
Figure 16: Connecting an External Load to DIO Pins
HIGH
LOW
P0 (SFR 0x80)
P0 (SFR80)
© 2008–2011 Teridian Semiconductor Corporation
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
44
BROWNOUT
1
MISSION
LCD/SLEEP
1
1
1
5
43
2
2
2
2
6
DIO
V3P3SYS
42
V3P3D
GNDD
3
VBAT
3
3
3
7
41
4
4
4
0
4
P1 (SFR 0x90)
P1 (SFR 0x90)
39
5
1
5
5
5
38
6
6
6
2
6
Recommended
HIGH-Z
37
HIGH
LOW
7
7
7
3
7
BROWNOUT
MISSION
LCD/SLEEP
36
8
0
8
0
4
P2 (SFR 0xA0)
P2 (SFR 0xA0)
LCD_MAP[15:8] (I/O RAM 0x240A)
35
9
1
9
1
5
DIO
V3P3SYS
VBAT
V3P3D
GNDD
10
34
10
2
2
6
11
33
11
3
3
7
12
32
12
4
0
4
P3 (SFR 0xB0)
P3 (SFR 0xB0)
13
31
13
5
1
5
14
30
14
6
2
6
v1.2
15
29
15
3
7
7