PTN3361BBS,518 NXP Semiconductors, PTN3361BBS,518 Datasheet
PTN3361BBS,518
Specifications of PTN3361BBS,518
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PTN3361BBS,518 Summary of contents
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PTN3361B HDMI/DVI level shifter with dongle detect support and active DDC buffer Rev. 02 — 7 October 2009 1. General description The PTN3361B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to ...
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... NXP Semiconductors MULTI-MODE DISPLAY SOURCE PCIe PHY ELECTRICAL TMDS coded TX data FF TMDS coded TX data FF TMDS coded TX data FF TMDS clock TX pattern FF DDC I CONFIGURATION Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1]. Fig 1. Typical application system diagram PTN3361B_2 Product data sheet ...
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... NXP Semiconductors 2. Features 2.1 High-speed TMDS level shifting I Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals I Pin-programmable pre-emphasis feature I TMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock) I TMDS level shifting operation ...
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... NXP Semiconductors 3. Applications I DisplayPort to HDMI adapters (must enable DDET) I DisplayPort to DVI adapters required to drive long cables 4. Ordering information Table 1. Ordering information Type number Package Name Description PTN3361BBS HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 PTN3361B_2 Product data sheet ...
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... NXP Semiconductors 5. Functional diagram Fig 2. PTN3361B_2 Product data sheet HDMI/DVI level shifter with dongle detect and DDC buffer OE_N input bias 50 50 IN_D4+ IN_D4 input bias 50 50 IN_D3+ IN_D3 input bias 50 50 IN_D2+ IN_D2 input bias 50 50 IN_D1+ IN_D1 HPD_SOURCE ( 3.3 V) DDC_EN ( ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. PTN3361B_2 Product data sheet HDMI/DVI level shifter with dongle detect and DDC buffer terminal 1 index area GND PES0 DDET 4 GND 5 6 REXT HPD_SOURCE 7 SDA_SOURCE 8 SCL_SOURCE 9 10 PES1 GND 12 Transparent top view HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation ...
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... NXP Semiconductors 6.2 Pin description Table 2. Symbol OE_N, IN_Dx and OUT_Dx signals OE_N IN_D4+ IN_D4 IN_D3+ IN_D3 IN_D2+ IN_D2 IN_D1+ PTN3361B_2 Product data sheet HDMI/DVI level shifter with dongle detect and DDC buffer Pin description Pin Type 25 3.3 V low-voltage CMOS single-ended ...
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... NXP Semiconductors Table 2. Symbol IN_D1 OUT_D4+ OUT_D4 OUT_D3+ OUT_D3 OUT_D2+ OUT_D2 OUT_D1+ OUT_D1 HPD and DDC signals HPD_SINK HPD_SOURCE 7 SCL_SOURCE 9 SDA_SOURCE 8 SCL_SINK SDA_SINK PTN3361B_2 Product data sheet HDMI/DVI level shifter with dongle detect and DDC buffer Pin description …continued Pin Type ...
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... NXP Semiconductors Table 2. Symbol DDC_EN Supply and ground [1] GND Feature control signals REXT DDET PES1 PES0 Miscellaneous n.c. [1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board ...
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... NXP Semiconductors 7. Functional description Refer to The PTN3361B level shifts four lanes of low-swing AC-coupled differential input signals to DVI and HDMI compliant open-drain current-steering differential output signals 1.65 Gbit/s per lane. Speed of operation and cable length drive may be extended (by using the programmable pre-emphasis feature 2.25 Gbit/s per lane. It has ...
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... NXP Semiconductors 7.1.2 Output Enable function (OE_N) When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully functional. Input termination resistors are enabled and the internal bias circuits are turned on. When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a high-impedance state and drive zero output current ...
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... NXP Semiconductors 7.1.4 Enable/disable truth table Table 3. HPD_SINK, OE_N and DDC_EN enabling truth table Inputs HPD_SINK OE_N DDC_EN [1] [2] LOW LOW LOW LOW LOW HIGH LOW HIGH LOW LOW HIGH HIGH HIGH LOW LOW HIGH LOW HIGH HIGH HIGH LOW HIGH ...
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... NXP Semiconductors 7.2 Analog current reference The REXT pin (pin analog current sense port used to provide an accurate current reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use resistor (1 % tolerance) connected between this terminal and GND is recommended external 10 k connected to GND or V value less than 10 k ...
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... NXP Semiconductors 7.5 Active DDC buffer with rise time accelerator The PTN3361B DDC channel, besides providing 3 level shifting, includes active buffering and rise time acceleration which allows meters bus extension for reliable DDC applications. While retaining all the operating modes and features of the ...
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... NXP Semiconductors 7.6.2 Read operation The slave device address of PTN3361B is 80h. PTN3361B will respond to a Read command to slave address 81h (PTN3361B will respond with an ACK to a Write command to address 80h). Following the Read command, the PTN3361B will respond with the contents of its internal ROM sequence of 16 bytes, for as long as the master continues to issue clock edges with an acknowledge after each byte. The 16-byte sequence represents the ‘ ...
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... NXP Semiconductors 7.7 Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL TRANSMITTER/ Fig 7. 7.7.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 8. Application design-in information 8.1 Dongle or cable adaptor detect discovery mechanism The PTN3361B supports the source-side dongle detect discovery mechanism described in VESA DisplayPort Interoperability Guideline Version 1.1 . When a source-side cable adaptor is plugged into a multi-mode source device that supports multiple standards such as DisplayPort, DVI and HDMI, a discovery mechanism is needed for the multi-mode source to confi ...
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... NXP Semiconductors 9. Limiting values Table 7. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol stg V ESD [1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. [2] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged-Device Model - Component level ...
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... NXP Semiconductors 11. Characteristics 11.1 Differential inputs Table 10. Differential input characteristics for IN_Dx signals Symbol Parameter [1] UI unit interval V differential input peak-to-peak voltage RX_DIFFp-p T receiver eye time RX_EYE V peak common-mode input voltage (AC) i(cm)M(AC input impedance RX_DC V bias receiver voltage RX(bias) Z single-ended input impedance ...
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... NXP Semiconductors 11.2 Differential outputs The level shifter’s differential outputs are designed to meet HDMI version 1.3 and DVI version 1.0 specifications. Table 11. Differential output characteristics for OUT_Dx signals Symbol Parameter V single-ended HIGH-level OH(se) output voltage V single-ended LOW-level OL(se) output voltage ...
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... NXP Semiconductors 11.4 OE_N, DDC_EN and DDET inputs Table 13. OE_N, DDC_EN and DDET input characteristics Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL I input leakage current LI [1] Measured with input at V maximum and V IH 11.5 DDC characteristics Table 14. ...
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... NXP Semiconductors 12. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 17. Acronym CDM CEC DDC DVI EMI ESD HBM HDMI HPD 2 I C-bus ...
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... NXP Semiconductors 15. Revision history Table 18. Revision history Document ID Release date PTN3361B_2 20091007 • Modifications: Table 11 “Differential output characteristics for OUT_Dx sentence PTN3361B_1 20090929 PTN3361B_2 Product data sheet HDMI/DVI level shifter with dongle detect and DDC buffer Data sheet status Change notice ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 High-speed TMDS level shifting . . . . . . . . . . . . 3 2.2 DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 HDMI dongle detect support 2.4 HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description ...