PTN3380BBS,518 NXP Semiconductors, PTN3380BBS,518 Datasheet
PTN3380BBS,518
Specifications of PTN3380BBS,518
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PTN3380BBS,518 Summary of contents
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PTN3380B DVI level shifter with voltage regulator Rev. 2 — 1 February 2011 1. General description The PTN3380B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a ...
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... NXP Semiconductors MULTI-MODE DISPLAY SOURCE PCIe PHY ELECTRICAL TMDS coded data TMDS coded data TMDS coded data TMDS clock pattern DDC I/O (I CONFIGURATION Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1]. Fig 1. Typical application system diagram PTN3380B ...
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... NXP Semiconductors 2. Features and benefits 2.1 High-speed TMDS level shifting Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals TMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock) Integrated 50 ...
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... NXP Semiconductors 3. Applications DisplayPort to DVI adapters For DisplayPort to HDMI adapters, use PTN3381B 4. Ordering information Table 1. Ordering information Type number Package Name Description PTN3380BBS HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 7 0.85 mm PTN3380B Product data sheet All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 5. Functional diagram Fig 2. PTN3380B Product data sheet OE_N input bias 50 Ω 50 Ω IN_D4+ IN_D4− input bias 50 Ω 50 Ω IN_D3+ IN_D3− input bias 50 Ω 50 Ω IN_D2+ IN_D2− input bias 50 Ω 50 Ω IN_D1+ IN_D1− HPD_SOURCE ( 3.3 V) DDC_EN ( 3.3 V) ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. PTN3380B Product data sheet terminal 1 index area GND n. n.c. 5 GND REXT 6 HPD_SOURCE 7 SDA_SOURCE 8 9 SCL_SOURCE 10 n. GND 12 Transparent top view HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation. For enhanced thermal, ...
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... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin OE_N, IN_Dx and OUT_Dx signals OE_N 25 IN_D4+ 48 IN_D4 47 IN_D3+ 45 IN_D3 44 IN_D2+ 42 IN_D2 41 IN_D1+ 39 IN_D1 38 OUT_D4+ 13 OUT_D4 14 OUT_D3+ 16 OUT_D3 17 OUT_D2+ 19 OUT_D2 20 PTN3380B Product data sheet ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin OUT_D1+ 22 OUT_D1 23 HPD and DDC signals HPD_SINK 30 HPD_SOURCE 7 SCL_SOURCE 9 SDA_SOURCE 8 SCL_SINK 28 SDA_SINK 29 DDC_EN 32 Supply and ground 2, 11, 15, 21 26, 33, 40, 46 [1] GND 1, 5, 12, 18, 24, 27, 31, 37, 43 Feature control signals REXT 6 Voltage regulator terminals ...
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... NXP Semiconductors 7. Functional description Refer to The PTN3380B level shifts four lanes of low-swing AC-coupled differential input signals to DVI and HDMI compliant open-drain current-steering differential output signals 1.65 Gbit/s per lane. It has integrated 50 termination resistors for AC-coupled differential input signals. An enable signal OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing power consumption ...
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... NXP Semiconductors 7.1.2 Output Enable function (OE_N) When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully functional. Input termination resistors are enabled and the internal bias circuits are turned on. When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a high-impedance state and drive zero output current ...
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... NXP Semiconductors 7.1.4 Enable/disable truth table Table 3. HPD_SINK, OE_N and DDC_EN enabling truth table Inputs HPD_SINK OE_N DDC_EN [1] [2] LOW LOW LOW LOW LOW HIGH LOW HIGH LOW LOW HIGH HIGH HIGH LOW LOW HIGH LOW HIGH HIGH HIGH LOW HIGH ...
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... NXP Semiconductors 7.2 Analog current reference The REXT pin (pin analog current sense port used to provide an accurate current reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use k resistor (1 % tolerance) connected between this terminal and GND is recommended. ...
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... NXP Semiconductors 9. Recommended operating conditions Table 5. Symbol I(AV) R ref(ext) I load C o(reg) C reg(ext) T amb [1] Input signals to these pins must be AC-coupled. [2] Operation without external reference resistor is possible but will result in reduced output voltage swing accuracy. For details, see [3] A ceramic capacitor with ESR < 100 m is recommended and should be placed close to the pin(s). ...
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... NXP Semiconductors 10. Characteristics 10.1 Differential inputs Table 7. Differential input characteristics for IN_Dx signals Symbol Parameter UI unit interval V differential input peak-to-peak voltage RX_DIFFp-p T receiver eye time RX_EYE V peak common-mode input voltage (AC) i(cm)M(AC input impedance RX_DC V bias receiver voltage RX(bias) Z single-ended input impedance ...
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... NXP Semiconductors 10.2 Differential outputs The level shifter’s differential outputs are designed to meet HDMI version 1.3 and DVI version 1.0 specifications. Table 8. Differential output characteristics for OUT_Dx signals Symbol Parameter V single-ended HIGH-level OH(se) output voltage V single-ended LOW-level OL(se) output voltage ...
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... NXP Semiconductors 10.4 OE_N, DDC_EN inputs Table 10. OE_N and DDC_EN input characteristics Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL I input leakage current LI [1] Measured with input at V maximum and V IH 10.5 DDC characteristics Table 11. DDC characteristics Symbol Parameter ...
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... NXP Semiconductors 11. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 5. For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 15. Acronym CDM DDC DVI ESD HBM HDMI HPD 2 I C-bus I/O PCIe TMDS PTN3380B Product data sheet maximum peak temperature = MSL limit, damage level ...
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... NXP Semiconductors 14. Revision history Table 16. Revision history Document ID Release date PTN3380B v.2 20110201 • Modifications: Section 1 “General – Second paragraph, third sentence changed from “needs only one external capacitor” to “needs only two external capacitors” – Sixth paragraph: changed from “(100 mW typical)” to “(100 mW typical with no load regulator)” ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 3 2.1 High-speed TMDS level shifting . . . . . . . . . . . . 3 2.2 DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2 voltage regulator . . . . . . . . . . . . . . . . . 3 2.5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description ...