TDA18218HN/C1,518 NXP Semiconductors, TDA18218HN/C1,518 Datasheet
TDA18218HN/C1,518
Specifications of TDA18218HN/C1,518
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TDA18218HN/C1,518 Summary of contents
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TDA18218HN DVB-T Silicon Tuner IC Rev. 01 — 8 July 2009 1. General description The TDA18218HN is a Silicon Tuner IC designed for digital terrestrial (DVB-T) TV reception. The TDA18218HN integrates the overall tuning function, including selectivity and provides a ...
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... NXP Semiconductors 4. Quick reference data Table 1. Quick reference data 3 output level option = p); IF output load = each terminal amb CC Symbol Parameter f RF frequency RF NF tuner noise figure tun phase noise n P power dissipation V maximum input voltage i(max) image rejection image S digital sensitivity ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. 7.2 Pin description Table 3. Symbol RF_IN i.c. i.c. GND(RF) i.c. i.c GND(IF) V CC(IF) i.c. CAPREG_VCO GND(VCO) V CC(PLL) GND(PLL) VTLO TDA18218HN_1 Product data sheet terminal 1 index area 1 RF_IN i. GND(RF) i.c. 5 i.c. 6 GND(IF CC(IF) i ...
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... NXP Semiconductors Table 3. Symbol CPLO XTAL_P XTAL_N i.c. XTO_P XTO_N XTAL_MS AS GND(IF) CP_K VT_K REG18 REG28 GND(IF) V CC(IF) IFO_N IFO_P VIFAGC i.c. GND(DIG) SCL SDA CAPRFAGC GND(RF) i.c. GND(RF) GND(RF) GND(RF) i.c. GND(RF) V CC(RF CC(RF) i.c. 8. Functional description The RF input signal is driven to a low-noise amplifier then amplified and fed to the image rejection mixer. The mixer down-converts the RF signal to a low IF frequency, which depends on channel bandwidth (standard IF fi ...
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... NXP Semiconductors and 8 MHz channel bandwidths). The TDA18218HN requires a single 16 MHz crystal for clock generation MHz differential sine wave clock reference is available to drive a channel decoder. 8.1 AGC1 stage The TDA18218HN embeds 2 different RF amplifiers with internal gain control. The first stage, AGC1, behaves like a LNA (Low noise amplifier); its gain can take 4 different values (15 dB and 6 dB). Purpose of this amplifi ...
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... NXP Semiconductors It should be noted that the level control is always operating. The strategy of the level detection has to be adapted for each type of channel decoder. It must be defined to satisfy ADC sampling (minimum level, ADC headroom). All AGC amplifiers are controlled independently. 8.4 Power-down mode The TDA18218HN can be programmed in Standby mode ...
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Table 4. I C-bus register map Sub Register address 7 (MSB) 6 Address byte Address byte 00h ID byte 1 01h Read byte 1 - LO_Lock 02h Read byte 2 03h Read byte ...
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Table 4. I C-bus register map …continued Sub Register address 7 (MSB) 6 13h Call divider byte 4 14h Call divider byte 5 15h Call divider byte 6 16h Call divider byte 7 17h Power-down - pdLT byte 1 ...
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Table 4. I C-bus register map …continued Sub Register address 7 (MSB) 6 28h IR CAL byte 1 29h IR CAL byte 2 2Ah IR CAL byte 3 2Bh IR CAL byte 4 2Ch RF CAL byte 1 2Dh ...
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... NXP Semiconductors 2 9.2 I C-bus address selection The programmable module address bits MA[1:0] allow up to four tuners to be addressed in one system. Bits MA[1:0] are programmed by applying a specific voltage (V AS. The relationship between the status of bits MA[1:0] and the voltage applied to pin AS is shown in Table 5 ...
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... NXP Semiconductors Table 8. Address 19h 9.4 Temperature sensor Table 9. Address Register 1Dh 01h [1] The die temperature can be read as shown in Table 10. TM_D[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 TDA18218HN_1 Product data sheet Crystal buffer output register bit descriptions ...
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... NXP Semiconductors Table 10. TM_D[3:0] 1101 1110 1111 9.5 Standby mode selection Table 11. Mode Device-off mode Standby mode with loop-through and crystal oscillator on (default at POR), XTOUT 1200 mV Standby mode with only crystal oscillator on 9.6 IF level Refer to 9.7 AGC and band-pass filters Table 12. ...
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... NXP Semiconductors 9.8 RFin to LT path Table 13. RFin to LT path bit descriptions Address Register Bit 20h AGC1 byte 1 3 04h Read byte LT[1:0] Table 14. Bit Manual_LT Pin XTAL_MS AGC1 and LT attenuator gain modes Table 15. LT[ 9.9 PLL settings Table 16. PLL bit descriptions ...
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... NXP Semiconductors 9.10 Power-down and switches Table 17. Power-down and switches bit descriptions Address Register 17h Power-down byte 1 18h Power-down byte 2 [1] This setting controls the status of the Low Noise Amplifier (LNA). [2] RFSW_MTO_LT_RFin = 0 in tuner applications with loop-through disabled. RFSW_MTO_LT_RFin = 1 in tuner applications with loop-through enabled. ...
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... NXP Semiconductors Table 18. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter stg ESD [1] Class III: 200 V to 1000 V. 11. Thermal characteristics Table 19. Symbol Parameter R th(j-a) T amb 12. Characteristics Table 20. Loop-through characteristics (RF input to loop-through output 3.3 V; unless otherwise specified. ...
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... NXP Semiconductors Table 21. General characteristics for TV reception (RF input to IF output 3 output level option p), IF output load = each pin; unless otherwise specified. amb CC Symbol Parameter V supply voltage CC I supply current CC P power dissipation f RF frequency RF f nominal IF frequency IF(nom) G voltage gain ...
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... NXP Semiconductors Table 21. General characteristics for TV reception (RF input to IF output 3 output level option p), IF output load = each pin; unless otherwise specified. amb CC Symbol Parameter t setting time set f tuner frequency (step size) tun(step) V maximum input voltage i(max) S digital sensitivity dig [1] XTAL buffer off. ...
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... NXP Semiconductors Table 22. Pin characteristics …continued 3.3 V; unless otherwise specified amb CC Symbol Parameter f SCL clock frequency SCL pin SDA V HIGH-level output voltage OH V LOW-level input voltage IL V HIGH-level input voltage IH [1] Typical value is HIGH impedance input. [2] Devices that use non-standard supply voltages, which do not conform to the intended I levels to the supply voltage to which the pull-up resistors are connected ...
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Application information 1 nF 150 BAV99W BLM18HK102SNI 150 pF RF_IN_OUT 1 H BAV99W BLM18HK102SNI +3V3_TUN 47 nF 470 pF CAPREG_VCO GND(VCO) 100 ...
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... NXP Semiconductors 14. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Abbreviations Table 23. Acronym ADC AGC BER BP Cxtal DVB-T DVR FCDM IC IF LNA LPFc LO LT MSB PCB PLL POR QAM RF RoHS SAW STB TOP VCO XTAL TDA18218HN_1 Product data sheet Abbreviations Description Analog-to-Digital Converter Automatic Gain Control Bit Error Rate ...
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... NXP Semiconductors 16. Revision history Table 24. Revision history Document ID Release date TDA18218HN_1 20090708 TDA18218HN_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 8 July 2009 TDA18218HN DVB-T Silicon Tuner IC Supersedes - © NXP B.V. 2009. All rights reserved ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Table 4. I C-bus register map . . . . . . . . . . . . . . . . . . . . .7 Table 5. Address byte 1 bit descriptions . . . . . . . . . . . .10 Table 6. Address byte 2 bit descriptions . . . . . . . . . . . .10 Table 7. ID byte bit descriptions . . . . . . . . . . . . . . . . . .10 Table 8. Crystal buffer output register bit descriptions .11 Table 9 ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Functional description . . . . . . . . . . . . . . . . . . . 4 8.1 AGC1 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 AGC2 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.3 IF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.4 Power-down mode . . . . . . . . . . . . . . . . . . . . . . 6 9 Control interface ...