TDA9989ET/C1,557 NXP Semiconductors, TDA9989ET/C1,557 Datasheet - Page 30

• Manufacturer Part Number: TDA9989ET/C1,557
• Description: IC HDMI TX 1.3A 150MHZ 64-TFBGA
• Manufacturer: NXP Semiconductors
• Type: Transmitterr

Specifications of TDA9989ET/C1,557

• Applications: Cameras, Cell Phones, Media Players
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935288146557

NXP Semiconductors
9. Input format
Table 23.
L: recommend tied to LOW voltage
TDA9989_2
Product data sheet
Input pins
Video port A
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
Video port B
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
Input format
Signal
Cb[0]/B[0]
Cb[1]/B[1]
Cb[2]/B[2]
Cb[3]/B[3]
Cb[4]/B[4]
Cb[5]/B[5]
Cb[6]/B[6]
Cb[7]/B[7]
Y[0]/G[0]
Y[1]/G[1]
Y[2]/G[2]
Y[3]/G[3]
Y[4]/G[4]
Y[5]/G[5]
8.3 ID version
8.4 Clock stretching
The CEC core does not need memory page mechanism due to its reduced number of
registers.
The ID version readable via I
and VERSION registers.The ID version value is 131h.
Clock stretching pauses a transaction by holding the CSCL line LOW. The transaction
cannot continue until the line is released HIGH again.
For example: on the byte level, a device may be able to receive bytes of data at a fast rate,
but needs more time to store a received byte or prepare another byte to be transmitted.
Slaves can then hold the CSCL line LOW after reception and acknowledgment of a byte to
force the master into a wait state until the slave is ready for the next byte transfer.see
Table 31
Clock stretching must be supported by I
TDA9989 is used. If CEC feature of TDA9989 is not used, I
to support clock stretching.
In
has been mapped to Y (YCbCr space)/G (RGB space) and VPC has been mapped to Cr
(YCbCr space)/R (RGB space).
Table 23
RGB
4 : 4 : 4
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
the port VPA has been mapped to Cb (YCbCr space)/B (RGB space), VPB
YCbCr
4 : 4 : 4
Cb[0]
Cb[1]
Cb[2]
Cb[3]
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Rev. 02 — 11 June 2009
2
C-bus is defined by the concatenation of VERSION_MSB
4 : 2 : 2 (semi-planar)
Y
Y
Y
Y
Cb[0]
Cb[1]
Cb[2]
Cb[3]
Y
Y
Y
Y
Y
Y
0
0
0
0
0
0
0
0
0
0
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
2
Y
Y
Y
Y
Cr[0]
Cr[1]
Cr[2]
Cr[3]
Y
Y
Y
Y
Y
Y
C-bus master especially when CEC feature of
1
1
1
1
1
1
1
1
1
1
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
HDMI 1.3a transmitter with CEC support
4 : 2 : 2 (ITU 656-like)
Cb[0]
Cb[1]
Cb[2]
Cb[3]
L
L
L
L
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Cb[8]
Cb[9]
2
C-bus master does not need
Y
Y
Y
Y
L
L
L
L
Y
Y
Y
Y
Y
Y
0
0
0
0
0
0
0
0
0
0
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
TDA9989
© NXP B.V. 2009. All rights reserved.
Cr[0]
Cr[1]
Cr[2]
Cr[3]
L
L
L
L
Cr[4]
Cr[5]
Cr[6]
Cr[7]
Cr[8]
Cr[9]
Y
Y
Y
Y
L
L
L
L
Y
Y
Y
Y
Y
Y
1
1
1
1
1
1
1
1
1
1
30 of 48
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]