74HC541DB,112 NXP Semiconductors, 74HC541DB,112 Datasheet - Page 14

• Manufacturer Part Number: 74HC541DB,112
• Description: IC BUFF/DVR TRI-ST 8BIT 20SSOP
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC541DB,112

• Package / Case: 20-SSOP
• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Current - Output High, Low: 7.8mA, 7.8mA
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: 74HC
• Number Of Channels Per Chip: 8
• Polarity: Non-Inverting
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 7.8 mA
• Input Bias Current (max): 8 uA
• Low Level Output Current: 7.8 mA
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 10 ns
• Number Of Lines (input / Output): 8 / 8
• Logical Function: Buffer/Line Driver
• Number Of Elements: 1
• Number Of Channels: 8
• Number Of Inputs: 8
• Number Of Outputs: 8
• Operating Supply Voltage (typ): 5V
• Package Type: SSOP
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2V
• Quiescent Current: 8uA
• Technology: CMOS
• Pin Count: 20
• Mounting: Surface Mount
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2710-5; 935180350112

Philips Semiconductors
AC waveforms 74HCT (continued)
Test circuit for 74HCT
March 1988
handbook, full pagewidth
handbook, full pagewidth
HCMOS family characteristics
Switch position
Note
1. For open-drain N-channel outputs t
TEST
t
t
t
t
C
R
PZH
PZL
PHZ
PLZ
L
T
=
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
SWITCH
GND
V
GND
V
CC
CC
LOW-to-OFF
OFF-to-LOW
HIGH-to-OFF
OFF-to-HIGH
MGK566
OUTPUT
OUTPUT
OUTPUT
ENABLE
GENERATOR
PULSE
Fig.11 Propagation delays of 3-state outputs.
90%
Fig.12 Test circuit for 3-state outputs.
PLZ
t f
1.3 V
10%
and t
V I
t PLZ
enabled
outputs
t PHZ
PZL
R T
are applicable.
10%
D.U.T
V CC
90%
14
o
of
disabled
outputs
V O
C L
t r
t PZL
t PZH
R L = 1 k
50 pF
FAMILY SPECIFICATIONS
1.3 V
MGK563
1.3 V
outputs
enabled
V CC