TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 164

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

9.5.6
9.5.5
9.5.9
9.5.7
9.5.8
Capture Registers (TB0CP0, TB0CP1)
Up-counter capture register (TB0UC)
Capture interrupt (INTCAP00, INTCAP01)
Comparators (CP0,CP1)
Timer Flip-flop (TB0FF0)
capture register, use a 16-bit data transfer instruction or read in the order of low-order bits
followed by high-order bits.
reading the TB0U
up-counter with set values of the TB0RG0 and TB0RG1 timer registers. If a match is detected,
INTTB00 and INTTB01 are generated.
signal to the capture registers.
TB0FFCR<TB0C1T1, TB0C0T1, TB0E1T1, TB0E0T1>.
writing “00” to TB0FFCR<TB0FF0C1:0>. It can be set to “1” by writing “01,” and can be cleared
to “0” by writing “10.”
enable timer output, the port A related registers PACR and PAFR1 must be programmed
beforehand.
the UC up-counter into the TB0CP0 and TB0CP1 capture registers. The interrupt setting is
specified by the CPU.
The value of TB0FF0 becomes undefined after a reset. The flip-flop can be reversed by
The TB0FF0 value can be output to the timer output pin:TB0OUT (shared with PA1). To
These are 16-bit registers for latching values from the UC up-counter. To read data from the
Other than th
These are 16-bit comparators for detecting a match by comparing set values of the UC
The timer flip-flop (TB0FF0) is reversed by a match signal from the comparator and a latch
Interrupts INTCAP00 and INTCAP01 can be generated at the timing of latching values from
e capturing functions shown above, the current count value of the UC can be captured by
C registers.
TMPM370 9-21
It can be enabled or disabled to reverse by setting the
16-bit Timer/Event Counters
TMPM370