TMPM370FYFG Toshiba, TMPM370FYFG Datasheet - Page 197

• Manufacturer Part Number: TMPM370FYFG
• Manufacturer: Toshiba

Specifications of TMPM370FYFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

③ Error Generation
UART Mode
I/O Interface Mode
Interrupt conditions are decided by the SC0TFC<TFIS> settings as described in Table
10-6.
Table 10-6 Transmit Interrupt conditions in use of FIFO
SC0TFC<TFIS>
Framing Error
Overrun Error
Parity Error
Overrun Error
Underrun Error
Writing FIFO
“0”
“1”
mode
"The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
"The fill level of FIFO" is smaller than or equal to "the fill level of FIFO intrruption
generation."
TMPM370 10-26
Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SC0CR<SCLKS>
setting.)
Immediately after the rising or falling edge of the next SCLK.
(Rising or falling is determined according to SC0CR<SCLKS>
setting.)
9 bits
-
Around the center of stop bit
Interrupt conditions
Around the center of parity bit
8bits ＋ Parity
7bits+Parity
7 bits
8 bits
Serial Channel
TMPM370