74HCT640DB,112 NXP Semiconductors, 74HCT640DB,112 Datasheet - Page 10

• Manufacturer Part Number: 74HCT640DB,112
• Description: IC TRANSCEIVER 3ST 8BIT 20SSOP
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT640DB,112

• Logic Type: Transceiver, Inverting
• Package / Case: 20-SSOP
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Current - Output High, Low: 6mA, 6mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: 74HCT
• Number Of Channels Per Chip: 8
• Input Level: TTL
• Output Level: TTL
• Output Type: 3-State
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Propagation Delay Time: 9 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Function: Inverting
• Input Bias Current (max): 8 uA
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Polarity: Inverting
• Number Of Circuits: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2896-5; 935190190112

Philips Semiconductors
HC TYPES
AC waveforms 74HC
AC waveforms 74HC
March 1988
handbook, full pagewidth
HCMOS family characteristics
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
(2) For AC measurements: t
Fig.4
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
OUTPUT
PRESET
CLOCK
RESET,
INPUT
INPUT
INPUT
r
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
INPUT
OUTPUT
10 %
50%
t su
t rem
50%
t r
10%
50%
t PLH
90%
t PHL
t THL
t WH
10%
max
90%
50%
90%
t h
, there is no constraint on t
t r
1/f max
t TLH
50%
90%
t f
50%
10%
10
t WL
t su
t f
t PHL
t PLH
t TLH
r
, t
f
with 50% duty factor.
MGK564
t h
FAMILY SPECIFICATIONS
t THL
V CC
GND
MGK569
V CC
GND
V CC
GND
V CC
GND