M25P64 STMicroelectronics, M25P64 Datasheet

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M25P64

Manufacturer Part Number
M25P64
Description
Manufacturer
STMicroelectronics
Datasheet

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Features
January 2007
64 Mbit of Flash memory
2.7 V to 3.6 V single supply voltage
SPI bus compatible serial interface
50 MHz clock rate (maximum)
V
(optional)
Page Program (up to 256 Bytes)
– in 1.4 ms (typical)
– in 0.35 ms (typical with V
Sector Erase (512 Kbit)
Bulk Erase (64 Mbit)
Electronic Signatures
– JEDEC standard two-Byte signature
– RES instruction, one-Byte, signature (16h),
Hardware Write Protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
More than 100 000 Erase/Program cycles per
sector
More than 20-year data retention
Packages
– ECOPACK® (RoHS compliant)
PP
(2017h)
for backward compatibility
= 9 V for Fast Program/Erase mode
PP
= 9 V)
64 Mbit, low voltage, Serial Flash memory
Rev 6
with 50 MHz SPI bus interface
8 × 6 mm (MLP8)
VDFPN8 (ME)
300 mils width
SO16 (MF)
M25P64
www.st.com
1/49
1

M25P64 Summary of contents

Page 1

... More than 100 000 Erase/Program cycles per sector More than 20-year data retention Packages – ECOPACK® (RoHS compliant) January 2007 64 Mbit, low voltage, Serial Flash memory with 50 MHz SPI bus interface = Rev 6 M25P64 VDFPN8 (ME) 8 × (MLP8) SO16 (MF) 300 mils width 1/49 www.st.com 1 ...

Page 2

... Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.4 Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 2/49 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 M25P64 ) . . . . . . . . . . . . 10 PP ...

Page 3

... M25P64 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE 6.11 Read Electronic Signature (RES Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 Package mechanical ...

Page 4

... Table 14. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 15. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4/49 M25P64 ...

Page 5

... M25P64 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10 ...

Page 6

... Description 1 Description The M25P64 Mbit ( Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. An enhanced Fast Program/Erase mode is available to speed up operations in factory environment ...

Page 7

... M25P64 W/V PP HOLD V SS Function Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect/Enhanced Program Supply Voltage Hold Supply Voltage Ground M25P64 W for package dimensions, and how to identify pin-1. Description Q AI07485B ...

Page 8

... Description Figure 3. SO connections Don’t Use 2. See Section 11: Package mechanical 8/49 M25P64 HOLD W/V PP for package dimensions, and how to identify pin-1. M25P64 AI07486C ...

Page 9

... M25P64 2 Signal description 2.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data Input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C) ...

Page 10

... stable until the Program/Erase algorithm is completed. 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS 10/49 it acts as an additional power supply pin. In this case V PPH supply voltage. CC M25P64 ) PP ) the pin is seen as a control CC must PP ...

Page 11

... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P64 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...

Page 12

... R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA 12/ µs <=> the application must ensure that the Bus p MSB M25P64 MSB AI01438B ...

Page 13

... M25P64 4 Operating features 4.1 Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory ...

Page 14

... Standby Power mode. The device consumption drops to I 4.6 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 6.4: Read Status Register 14/49 (RDSR). M25P64 . CC1 ...

Page 15

... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P64 features the following data protection mechanisms: Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...

Page 16

... To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Figure 6. Hold condition activation C HOLD 16/49 Figure 6). Hold Condition (standard use) M25P64 Figure 6). Hold Condition (non-standard use) AI02029D ...

Page 17

... M25P64 5 Memory organization The memory is organized as: 8388608 bytes (8 bits each) 128 sectors (512Kbits, 65536 bytes each) 32768 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...

Page 18

... M25P64 7FFFFFh 7EFFFFh 7DFFFFh 7CFFFFh 7BFFFFh 7AFFFFh 79FFFFh 78FFFFh 77FFFFh 76FFFFh 75FFFFh 74FFFFh 73FFFFh 72FFFFh 71FFFFh 70FFFFh 6FFFFFh 6EFFFFh 6DFFFFh 6CFFFFh ...

Page 19

... M25P64 Table 3. Memory organization (continued) Sector Address range 5C0000h 5B0000h 5A0000h 590000h 580000h 570000h 560000h 550000h 540000h 530000h 520000h 510000h 500000h 4F0000h 4E0000h 4D0000h ...

Page 20

... M25P64 39FFFFh 38FFFFh 37FFFFh 36FFFFh 35FFFFh 34FFFFh 33FFFFh 32FFFFh 31FFFFh 30FFFFh 2FFFFFh 2EFFFFh 2DFFFFh 2CFFFFh 2BFFFFh 2AFFFFh 29FFFFh 28FFFFh 27FFFFh 26FFFFh ...

Page 21

... M25P64 Table 3. Memory organization (continued) Sector Address range 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h ...

Page 22

... Table 4. One-byte instruction Description code 0000 0110 0000 0100 1001 1111 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1010 1011 M25P64 Address Dummy Data bytes bytes bytes 06h 0 0 04h 0 0 9Fh ...

Page 23

... M25P64 6.1 Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High ...

Page 24

... Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Figure 9. Write Disable (WRDI) instruction sequence 24/49 (Figure 9) resets the Write Enable Latch (WEL) bit Instruction D High Impedance AI03750D M25P64 ...

Page 25

... M25P64 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (17h) ...

Page 26

... BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0. 26/ BP2 Figure 11. BP1 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit Table 2) becomes M25P64 b0 WIP ...

Page 27

... M25P64 6.4.4 SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/V ) signal. The Status Register Write Disable (SRWD) bit and Write Protect PP (W/V ) signal allow the device to be put in the Hardware Protected mode (when the Status PP Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/V ...

Page 28

... Protected area Unprotected area Protected against Ready to accept Page Program, Page Program and Sector Erase and Sector Erase Bulk Erase instructions Protected against Ready to accept Page Program, Page Program and Sector Erase and Sector Erase Bulk Erase instructions Table 7. M25P64 ) is (1) ...

Page 29

... M25P64 When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless ...

Page 30

... C D High Impedance Q 1. Address bit A23 is Don’t Care. 30/49 Figure 13 Instruction 24-Bit Address MSB Data Out MSB M25P64 Data Out 2 7 AI03748D ...

Page 31

... M25P64 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...

Page 32

... Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see 32/49 Figure 15. Table 2 and Table 3) is not executed. M25P64 Table 14: AC ...

Page 33

... M25P64 Figure 15. Page Program (PP) instruction sequence MSB Instruction 24-Bit Address MSB Data Byte 2 Data Byte MSB ...

Page 34

... Figure 16. Sector Erase (SE) instruction sequence Address bit A23 is Don’t Care. 34/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 16. Table 2 and Table 3) is not executed Instruction 23 22 MSB Bit Address AI03751D M25P64 ) is ...

Page 35

... M25P64 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...

Page 36

... Figure 18. Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P64, is 16h. 36/49 Figure 18 Dummy Bytes ...

Page 37

... M25P64 7 Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay Power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included ...

Page 38

... Time delay to Write instruction PUW (1) V Write Inhibit Voltage WI 1. These parameters are characterized only. 38/49 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL tPUW Parameter M25P64 Read Access allowed Device fully accessible time AI04009C Min. Max. Unit 1.5 2.5 µ ...

Page 39

... M25P64 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device outside the ratings listed in the device ...

Page 40

... Test condition V OUT °C and a frequency of 20 MHz. A Min. Typ Max. 2.7 3.6 8.5 9.5 – Min. Max 0. 0. Input and Output 0.7V CC 0.5V CC 0.3V CC AI07455 Min. Max M25P64 Unit V V °C °C Unit Unit pF pF ...

Page 41

... M25P64 Table 13. DC characteristics Symbol I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating Current (WRSR) CC5 I Operating Current (SE) CC6 I Operating Current (BE) CC7 Operating current for Fast I CCPP Program/Erase mode V Operating current in ...

Page 42

... Table 11 Min. Typ. Max. D. 0.1 0 100 100 200 5 15 1.4 0.4+ n*1/256 0.35 1 0.5 68 160 35 160 M25P64 Unit MHz MHz ns ns V/ns V/ ...

Page 43

... M25P64 Figure 21. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 22. Write Protect setup and hold timing during WRSR when SRWD = 1 W/V PP tWHSL High Impedance Q tSLCH tCHSH tCHDX tCLCH MSB IN DC and AC parameters tSHSL tSHCH tCHCL LSB IN AI01447C tSHWL AI07439b 43/49 ...

Page 44

... Figure 24. Output timing S C tCLQV tCLQX tCLQX Q ADDR D LSB IN Figure 25. V PPH PPH W/V PP 44/49 tCHHL tHLQZ tCLQV timing PP, SE, BE tVPPHSL tHLCH tHHCH tCHHH tHHQX tCH tCL LSB OUT tQLQH tQHQL End of PP (identified by WPI polling) M25P64 AI02032 tSHQZ AI01449e ai12092 ...

Page 45

... M25P64 11 Package mechanical Figure 26. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 15. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm, ...

Page 46

... Typ Min Max 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 – – 10.00 10.65 0.25 0.75 0.40 1.27 0° 8° 0. 45˚ ddd inches Typ Min 0.093 0.004 0.013 0.009 0.398 0.291 0.050 – 0.394 0.010 0.016 0° M25P64 Max 0.104 0.012 0.020 0.013 0.413 0.299 – 0.419 0.030 0.050 8° 0.004 ...

Page 47

... ST Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Part numbering M25P64 – 47/49 ...

Page 48

... Page Programming, characteristics. added and Power-up specified for Fast section. W pin 2 inserted below Figure 26 Blank option and Figure 25: V Section 11: modified. Table 13: DC characteristics. Features on page ground descriptions added. SS updated and reset. added in Table 9: Absolute maximum data. M25P64 Page timing PPH 1. ...

Page 49

... M25P64 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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