M35080 STMicroelectronics, M35080 Datasheet

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M35080

Manufacturer Part Number
M35080
Description
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
The M35080 device consists of 1024x8 bits of low
power
STMicroelectronics’ proprietary High Endurance
Double Polysilicon CMOS technology.
The device is accessed by a simple SPI-compati-
ble serial interface. The bus signals consist of a
serial clock input (C), a serial data input (D) and a
serial data output (Q), as shown in Table 1.
The device is selected when the chip select input
(S) is held low. Data is clocked in during the low to
high transition of the clock, C. Data is clocked out
during the high to low transition of the clock.
Table 1. Signal Names
June 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
C
D
Q
S
W
V
V
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
Single Supply Voltage: 4.5 V to 5.5 V
5 MHz Clock Rate (maximum)
Sixteen 16-bit Incremental Registers
BYTE and PAGE WRITE (up to 32 Bytes)
(except for the Incremental Registers)
Self-Timed Programming Cycle
Hardware Protection of the Status Register
Resizeable Read-Only EEPROM Area
Enhanced ESD Protection
1 Million Erase/Write Cycles (minimum)
40 Year Data Retention (minimum)
CC
SS
EEPROM,
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Supply Voltage
Ground
fabricated
with
8 Kbit Serial SPI Bus EEPROM
Figure 1. Logic Diagram
With Incremental Registers
W
D
C
S
0.25 mm frame
V CC
8
PSDIP8 (BN)
150 mil width
8
V SS
SO8 (MN)
M35080
1
1
PRELIMINARY DATA
M35080
Q
AI02143
1/18

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M35080 Summary of contents

Page 1

... Hardware Protection of the Status Register Resizeable Read-Only EEPROM Area Enhanced ESD Protection 1 Million Erase/Write Cycles (minimum) 40 Year Data Retention (minimum) DESCRIPTION The M35080 device consists of 1024x8 bits of low power EEPROM, fabricated STMicroelectronics’ proprietary High Endurance Double Polysilicon CMOS technology. The device is accessed by a simple SPI-compati- ble serial interface ...

Page 2

... M35080 Figure 2. DIP and SO Connections M35080 AI02144B Note Not Connected. The memory is organized in pages of 32 bytes. However, the first page is not treated in the same way as the others. Instead considered to con- sist of sixteen 16-bit incremental registers. Each ...

Page 3

... SRWD UV Note: 1. BP0, BP1: Read and write bits 2. UV, INC, WEL, WIP: Read only bits. 3. SRWD: Read and Write bit. MSB M35080 Data Bytes Unprotected Area Writeable (if the WREN instruction has set the WEL bit) Writeable (if the WREN instruction has set the ...

Page 4

... M35080 Figure 4. EEPROM and SPI Bus D SPI Interface with (CPOL, CPHA ('0', '0') or ('1', '1') C Master (ST6, ST7, ST9, ST10, Others) CS3 CS2 CS1 OPERATIONS All instructions, addresses and data are shifted se- rially in and out of the chip (along the bus, as shown in Figure 4). The most significant bit is pre- ...

Page 5

... During a Write operation (whether the memory area or to the status register), all bits of the status register remain valid, and can be read using the RDSR instruction. However, during a Write operation, the values of the non-volatile bits Protection M35080 DATA OUT ...

Page 6

... M35080 Figure 6. RDSR: Read Status Register Sequence INSTRUCTION D HIGH IMPEDANCE Q (SRWD, BP0, BP1) become frozen at a constant value. The updated value of these bits becomes available when a new RDSR instruction is execut- ed, after completion of the write cycle. On the oth- er hand, the two read-only bits (WEL, WIP) are dynamically updated during internal write cycles ...

Page 7

... Chip Select (S) must remain low throughout the operation, as shown in Figure 9. The device must be deselected just after the eighth bit of the data byte has been latched in, M35080 Array Addresses Protected M35080 1 none 0300h - 03FFh 0200h - 03FFh by a pull- ...

Page 8

... M35080 Figure 8. Write Enable Latch Sequence shown in Figure 9, otherwise the write process is cancelled. As soon as the memory device is de- selected, the self-timed internal write cycle is initi- ated. While the write is in progress, the status register may be read to check the status of the SR- WD, BP1, BP0, WEL and WIP bits. In particular, WIP contains a ‘ ...

Page 9

... Accesses to the memory array are ignored dur- ing the non-volatile programming cycle, and the programming cycle continues unaffected. – After execution of a WREN, WRDI, or RDSR in- struction, the device enters a wait state, and waits to be deselected. – Invalid S transitions are ignored. M35080 DATA BYTE ...

Page 10

... M35080 Figure 11. Block Diagram W Control Logic Address Register and Counter Note the top address of the memory. 10/18 High Voltage Generator I/O Shift Register Data Register & Comparators Bytes 0000h Incremental Register X Decoder Status Register Size of the An Read only EEPROM ...

Page 11

... FFh. The first 32 bytes are set to all ‘0’s, and hence the first 16 words at 0000h. The status register bits are initialized to ‘0’, except for bit b4, which is set to ‘1’, as shown in Table 8. M35080 DATA BYTE 1 7 ...

Page 12

... M35080 Table 9. DC Characteristics ( 70° C, –40 to 85°C or –40 to 125° Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current CC I Standby Current CC1 V Input Low Voltage IL V Input High Voltage IH 1 Output Low Voltage ...

Page 13

... CL 2. Value guaranteed by characterization, not 100% tested in production 4.5V to 5.5V 70° C, Parameter –40 to 85°C A Min D.C. 100 100 200 100 200 0 M35080 M35080 V = 4.5V to 5.5V, CC Unit T = –40 to 125°C A Max Min Max 5 D.C. 2.1 MHz 100 ns 100 ns 200 ns 200 ...

Page 14

... M35080 Figure 14. Serial Input Timing S tCHSL C tDVCH MSB IN D HIGH IMPEDANCE Q Figure 15. Output Timing S C tCLQX Q ADDR.LSB IN D 14/18 tSLCH tCHSH tCHDX tCLCH LSB IN tDLDH tDHDL tCH tCLQV tSHSL tSHCH tCHCL AI01447 tCL tSHQZ LSB OUT tQLQH tQHQL AI01449B ...

Page 15

... ST Sales Office nearest to you. Table 13. Ordering Information Scheme Example: M35080 Package BN PSDIP8 (0.25 mm frame) MN SO8 (150 mil width) Temperature Range 6 –40 ° °C –40 ° 125 °C 3 – M35080 Option T Tape and Reel Packing 15/18 ...

Page 16

... M35080 Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame Symb. Typ 7. 2. Figure 16. PSDIP8 (BN Note: 1. Drawing is not to scale. 16/18 mm Min. Max. Typ. 3.90 5.90 0.49 – 3.30 5.30 0.36 0.56 1.15 1.65 0.20 0.36 9.20 9.90 – – 0.300 6.00 6.70 – – 0.100 7.80 – 10.00 3.00 3. ...

Page 17

... Note: 1. Drawing is not to scale. mm Min. Max. Typ. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 – – 0.050 5.80 6.20 0.25 0.50 0.40 0.90 0° 8° M35080 inches Min. Max. 0.053 0.069 0.004 0.010 0.013 0.020 0.007 0.010 0.189 0.197 0.150 0.157 – – 0.228 0.244 0.010 0.020 0.016 0.035 0° 8° 8 0.004 h x 45˚ 17/18 ...

Page 18

... M35080 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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