MT48LC64M8A2P Micron Semiconductor Products, MT48LC64M8A2P Datasheet
MT48LC64M8A2P
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MT48LC64M8A2P Summary of contents
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Synchronous DRAM Module MT8LSDT6464A – 512MB MT16LSDT12864A – 1GB For the latest data sheet, refer to Micron’s Web site: Features • PC100- and PC133-compliant • 168-pin, dual in-line memory module (DIMM) • Utilizes 125 MHz and 133 MHz SDRAM components ...
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Table 3: Part Numbers Part Numbers MT8LSDT6464AG-13E_ MT8LSDT6464AY-13E_ MT8LSDT6464AG-133_ MT8LSDT6464AY-133_ MT16LSDT12864AG-13E_ MT16LSDT12864AY-13E_ MT16LSDT12864AG-133_ MT16LSDT12864AY-133_ Notes: 1. The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT8LSDT6464AG-133B1. ...
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Pin Assignments and Descriptions Table 4: Pin Assignment 168-Pin DIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Table 4 on page 3 for pin number and symbol information. Pin Numbers Symbol 27, 111, 115 RAS#, CAS#, WE# 42, 79, 125, 163 CK0–CK3 63, 128 ...
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... All resistor values are 10Ω unless otherwise specified. Per industry standard, Micron modules use various component speed grades as refer- enced in the module part numbering guide at: www.micron.com/numberguide. Standard modules use the following SDRAM devices: MT48LC64M8A2TG. Lead-free modules use the following SDRAM devices: MT48LC64M8A2P . Figure 3: Single Rank RAS# ...
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Figure 4: Dual Rank S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 ...
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General Description The MT8LSDT6464A and MT16LSDT12864A are high-speed CMOS, dynamic random- access, 512MB and 1GB memory modules organized in a x64 configuration. These mod- ules use internally configured quad-bank SDRAMs with a synchronous interface (all sig- nals are registered on ...
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INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least ...
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Figure 5: Mode Register Definition Diagram M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. PDF: 09005aef8088b2e3/Source: 09005aef8088077a SD8_16C64_128x64AG.fm - Rev. C 6/05 EN 512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM A12 A11 A10 A8 ...
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Table 6: Burst Definition Table Burst Length Full Page Notes: 1. For full-page accesses 2,048. 2. For A1–A9, A11 select the block of two burst; A0 selects the starting column within the block. 3. For ...
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Figure 6: CAS Latency Diagram COMMAND COMMAND Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of ...
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Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use and/or test modes. The pro- grammed burst length applies to ...
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Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and oper- ations, refer to the 512Mb SDRAM component data sheet. Table 8: ...
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Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections ...
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I Specifications and Conditions DD Table 12: I Specifications and Conditions – 512MB DD Notes 11, 13; notes appear on page 18; V Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE (MIN) ...
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Capacitance Table 14: Capacitance – 512MB Note 2; notes appear on page 18 Parameter Input capacitance: Address and command Input capacitance: CK Input capacitance: S# Input capacitance: CKE Input capacitance: DQMB Input/Output capacitance: DQ Table 15: Capacitance – 1GB Note ...
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Table 16: Electrical Characteristics and Recommended AC Operating Conditions (continued) Notes 11, 31; notes appear on page 18 Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters AC Characteristics Parameter ...
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Notes 1. All voltages referenced This parameter is sampled. V 1.4V MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications ...
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The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including used to reduce the data rate. 24. Auto precharge ...
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Serial Presence Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, and ...
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Figure 8: Definition of Start and Stop SCL SDA Figure 9: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first ...
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Figure 10: SPD EEPROM Timing Diagram SCL t SU:STA SDA IN SDA OUT Table 20: SERIAL Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic ...
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Table 21: Serial Presence-Detect EEPROM AC Operating Conditions (continued) All voltages referenced to V Parameter/Condition Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes avoid spurious start and stop conditions, a minimum ...
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Table 22: Serial Presence-Detect Matrix V = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” DD Byte Description 0 Number of bytes used by Micron 1 Total number of SPD memory bytes 2 Memory type 3 Number of ...
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Table 22: Serial Presence-Detect Matrix (continued +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” DD Byte Description 41 Device minimum active/auto-refresh time, 42-61 Reserved 62 SPD revision 63 Checksum for bytes 0–62 64 Manufacturer’s JEDEC ID ...
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Module Dimensions Figure 11: 168-Pin DIMM Dimensions – 512MB U1 U2 0.079 (2.00) R (2X) 0.118 (3.00) (2X) 0.118 (3.00) TYP .118 (3.00) TYP 2.625 (66.68) PIN 1 (PIN 85 ON BACKSIDE) 0.079 (2.00) R (2X 0.118 (3.00) ...
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Figure 12: 168-Pin DIMM Dimensions – 1GB U1 U2 0.079 (2.00) R (2X) 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.118 (3.00) TYP PIN 1 U11 U12 PIN 168 0.079 (2.00) R (2X 0.118 (3.00) 0(2X) .118 (3.00) TYP ...
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S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their ...