74LCXH162244MTX Fairchild Semiconductor, 74LCXH162244MTX Datasheet

IC BUFF DVR 16BIT LOW V 48TSSOP

74LCXH162244MTX

Manufacturer Part Number
74LCXH162244MTX
Description
IC BUFF DVR 16BIT LOW V 48TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXHr
Datasheet

Specifications of 74LCXH162244MTX

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
12mA, 12mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2005 Fairchild Semiconductor Corporation
74LCXH162244MEA
74LCXH162244MEX
74LCXH162244MTD
74LCXH162244MTX
74LCXH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26: Series Resistors in Outputs
General Description
The LCXH162244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The LCXH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
In addition, the outputs include equivalent 26
series resistors to reduce overshoot and undershoot and
are designed to sink/source up to 12 mA at V
The LCXH162244 is designed for low voltage (2.5V or
3.3V) V
signal environment.
The LCXH162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Code:
Order Number
CC
applications with capability of interfacing to a 5V
Package Number
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
CC
:
DS500249
(nominal)
3.0V.
Features
5V tolerant control inputs and outputs
2.3V–3.6V V
Outputs include equivalent series resistance of 26
make external termination resistors unnecessary and
reduce overshoot and undershoot
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
5.3 ns t
Power down high impedance inputs and outputs
r
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
12 mA output drive (V
Human body model
Machine model
Package Description
PD
max (V
CC
specifications provided
CC
!
200V
!
3.0V), 20
CC
2000V
3.0V)
September 2000
Revised May 2005
P
A I
CC
www.fairchildsemi.com
max
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to

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74LCXH162244MTX Summary of contents

Page 1

... Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LCXH162244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 74LCXH162244MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] © 2005 Fairchild Semiconductor Corporation Features 5V tolerant control inputs and outputs 2.3V– ...

Page 2

Connection Diagram www.fairchildsemi.com Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW –I Bushold Inputs –O Outputs ...

Page 3

Truth Tables Inputs OE I – Inputs OE I – HIGH Voltage Level L LOW Voltage Level Functional Description The LCXH162244 ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output ...

Page 5

DC Electrical Characteristics Symbol Parameter I Input Leakage Current Data I Control I Bushold Input Minimum I(HOLD) Drive Hold Current I Bushold Input Over-Drive I(OD) Current to Change State I 3-STATE Output Leakage OZ I Power-Off Leakage Current OFF I ...

Page 6

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C 6V for V V Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; f =1MHz, ...

Page 7

Schematic Diagram Generic for LCXH Family 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide www.fairchildsemi.com Package Number MS48A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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