74HC365N,652 NXP Semiconductors, 74HC365N,652 Datasheet - Page 13
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74HC365N,652
Manufacturer Part Number
74HC365N,652
Description
IC BUFF DVR TRI-ST HEX 16PDIP
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HCT365N652.pdf
(7 pages)
Specifications of 74HC365N,652
Package / Case
16-DIP (0.300", 7.62mm)
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
6
Current - Output High, Low
7.8mA, 7.8mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Logic Family
HC
Number Of Channels Per Chip
6
Polarity
Non-Inverting
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 7.8 mA
Input Bias Current (max)
8 uA
Low Level Output Current
7.8 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
95 ns @ 2 V or 19 ns @ 4.5 V or 16 ns @ 6 V
Number Of Lines (input / Output)
6 / 6
Logical Function
Buffer/Line Driver
Number Of Elements
1
Number Of Channels
6
Number Of Inputs
6
Number Of Outputs
6
Operating Supply Voltage (typ)
5V
Package Type
PDIP
Operating Supply Voltage (max)
6V
Operating Supply Voltage (min)
2V
Quiescent Current
8uA
Technology
CMOS
Pin Count
16
Mounting
Through Hole
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1435-5
74HC365N
933669580652
74HC365N
933669580652
Philips Semiconductors
AC waveforms 74HCT
Test circuit for 74HCT
March 1988
handbook, full pagewidth
HCMOS family characteristics
C
R
(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals
(2) For AC measurements: t
Fig.9
L
T
(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual
active levels of the forcing signals are specified in the individual device data sheet.
=
=
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
load capacitance including jig and probe capacitance (see AC
CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
OUTPUT
PRESET
CLOCK
RESET,
r
INPUT
INPUT
INPUT
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
GENERATOR
10%
1.3 V
PULSE
t su
t rem
1.3 V
t r
10%
1.3 V
t PLH
90%
t WH
max
Fig.10 Test circuit.
1.3 V
V I
90%
t h
, there is no constraint on t
1/f max
t TLH
t f
R T
13
t WL
o
D.U.T
V CC
t su
of
t PHL
V O
r
, t
f
with 50% duty factor.
C L
t h
FAMILY SPECIFICATIONS
t THL
MGK565
50 pF
MGK568
3 V
GND
3 V
GND
3 V
GND