A43L0616AV-5.5 AMIC Technology, Corp., A43L0616AV-5.5 Datasheet - Page 27

• Manufacturer Part Number: A43L0616AV-5.5
• Description: 5.5ns 183MHz CL=3 512K x 16-Bit x 2banks synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

(May, 2001, Version 1.0)
Page Read & Write Cycle at Same Bank @Burst Length=4
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
CKE
RAS
CAS
DQM
CS
DQ
DQ
WE
BA
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
0
Row Active
(A-Bank)
Ra
Ra
2. Row precharge will interrupt writing. Last data input, t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
1
command to avoid bus contention.
before end of burst. Input data after Row precharge cycle will be masked internally.
2
t
RCD
3
(A-Bank)
Ca0
Read
4
5
(A-Bank)
Read
Qa0
Cb0
6
Qa1
Qa0
7
Qb0
Qa1
*Note 2
8
*Note1
Qb0
Qb1
9
26
High
RDL
10
(A-Bank)
before Row precharge, will be written.
Write
Dc0
Dc0
Cc0
11
Dc1
Dc1
12
t
CDL
(A-Bank)
Dd0
Dd0
Write
Cd0
13
Dd1
Dd1
14
*Note3
t
*Note 2
RDL
AMIC Technology, Inc.
15
Precharge
(A-Bank)
16
A43L0616A
17
: Don't care
18
19