A43L0616AV-5.5 AMIC Technology, Corp., A43L0616AV-5.5 Datasheet - Page 36

• Manufacturer Part Number: A43L0616AV-5.5
• Description: 5.5ns 183MHz CL=3 512K x 16-Bit x 2banks synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

CLOCK
A10/AP
ADDR
RAS
CAS
(CL=2)
(CL=3)
CKE
Burst Read Single Bit Write Cycle @Burst Length=2, BRSW
BA
DQM
(May, 2001, Version 1.0)
CS
DQ
DQ
WE
0
Row Active
(A-Bank)
* Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).
RAa
RAa
1
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
2
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
The next cycle starts the precharge.
3
(A-Bank)
Write
DAa0
DAa0
CAa
4
Row Active
(B-Bank)
RBb
RBb
Auto Precharge
5
Read with
(A-Bank)
CAb
6
7
QAb0
8
QAb0
QAb1
9
High
35
QAb1
10
Row Active
(A-Bank)
RAc
RAc
Auto Precharge
11
Write with
(B-Bank)
DBc0
DBc0
CBc
12
* Note 2
13
(A-Bank)
Read
CAd
14
AMIC Technology, Inc.
15
QAd0
16
QAd1
QAd0
A43L0616A
17
Precharge
(A-Bank)
QAd1
: Don't care
18
19